From patchwork Mon Sep 21 02:13:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 7227161 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 88A2B9F372 for ; Mon, 21 Sep 2015 02:28:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CAA0820A14 for ; Mon, 21 Sep 2015 02:28:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 19A4420810 for ; Mon, 21 Sep 2015 02:28:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755864AbbIUC2W (ORCPT ); Sun, 20 Sep 2015 22:28:22 -0400 Received: from mail-by2on0087.outbound.protection.outlook.com ([207.46.100.87]:31760 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755795AbbIUC2U (ORCPT ); Sun, 20 Sep 2015 22:28:20 -0400 Received: from CH1PR03CA005.namprd03.prod.outlook.com (10.255.156.150) by BN3PR03MB1495.namprd03.prod.outlook.com (10.163.35.146) with Microsoft SMTP Server (TLS) id 15.1.274.16; Mon, 21 Sep 2015 02:13:40 +0000 Received: from BN1AFFO11FD036.protection.gbl (10.255.156.132) by CH1PR03CA005.outlook.office365.com (10.255.156.150) with Microsoft SMTP Server (TLS) id 15.1.274.16 via Frontend Transport; Mon, 21 Sep 2015 02:13:39 +0000 Authentication-Results: spf=softfail (sender IP is 66.35.236.227) smtp.mailfrom=altera.com; vger.kernel.org; dkim=none (message not signed) header.d=none; vger.kernel.org; dmarc=none action=none header.from=altera.com; Received-SPF: SoftFail (protection.outlook.com: domain of transitioning altera.com discourages use of 66.35.236.227 as permitted sender) Received: from sj-itexedge03.altera.priv.altera.com (66.35.236.227) by BN1AFFO11FD036.mail.protection.outlook.com (10.58.52.240) with Microsoft SMTP Server (TLS) id 15.1.274.4 via Frontend Transport; Mon, 21 Sep 2015 02:13:39 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by webmail.altera.com (66.35.236.227) with Microsoft SMTP Server (TLS) id 14.3.174.1; Sun, 20 Sep 2015 19:13:08 -0700 Received: from leyfoon-vm (pg-lftan-l.altera.com [137.57.103.123]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with SMTP id t8L2DVEV023916; Sun, 20 Sep 2015 19:13:32 -0700 (PDT) Received: by leyfoon-vm (sSMTP sendmail emulation); Mon, 21 Sep 2015 10:13:30 +0800 From: Ley Foon Tan To: Bjorn Helgaas , Russell King , Marc Zyngier CC: Arnd Bergmann , Dinh Nguyen , , , , , , Ley Foon Tan , , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , "Kumar Gala" , Lorenzo Pieralisi Subject: [PATCH v7 3/6] pci:host: Add Altera PCIe host controller driver Date: Mon, 21 Sep 2015 10:13:04 +0800 Message-ID: <1442801587-3812-4-git-send-email-lftan@altera.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1442801587-3812-1-git-send-email-lftan@altera.com> References: <1442801587-3812-1-git-send-email-lftan@altera.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BN1AFFO11FD036; 1:cxfO2AHKcp9vqaSqkZIRGQ4D3Jq3FfKOAiydO44aTwqDUCtObYg/E0Hp9bsGY+qN0vbi/BGhtMZ8UTEWD4TINwgnx1wf8Hge9uQ1sde9PYWWdfzFGLaJWOBxObv3HgckiwSgnukgVQH8OtCcnKyzYK6MAU4whsXh03olXmfYsyB10wUJRXbfp1r2032trEOSqqycrlt2ayGjLq1oL36cZRV+8v9Opq7IcCO5K9k05unPMiKcMhLcc+MbuvYc4GJo+DsvAbvw8F0d62sb41C8J+ayhWHvraKAFdC2rNQl+dTke7Icv0cdC3LdnZTiZA6/1Q1L33ZFSRXbcI/hbh5ojO5rHeqP4kty97NCbXzwbb8928gG4tLhZMe37H7QETEm X-Forefront-Antispam-Report: CIP:66.35.236.227; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(189002)(199003)(77156002)(62966003)(48376002)(86362001)(92566002)(6806004)(50226001)(2950100001)(33646002)(19580405001)(19580395003)(50466002)(50986999)(5890100001)(15975445007)(42186005)(5007970100001)(5001960100002)(68736005)(46102003)(11100500001)(36756003)(5001770100001)(87936001)(76176999)(5001860100001)(5001830100001)(229853001)(189998001)(106466001)(97736004)(64706001)(105596002)(4001540100001)(5003940100001)(47776003)(81156007)(7099028)(2004002); DIR:OUT; SFP:1101; SCL:1; SRVR:BN3PR03MB1495; H:sj-itexedge03.altera.priv.altera.com; FPR:; SPF:SoftFail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BN3PR03MB1495; 2:u6aEtiVWIlB6FFPg9lcgdq2L6uinPy5t4JBXIcins4FPpeVotjv7qPE/YREylOYb9zhD+p5lbfBHQPNeilau09xCFQJcxq6wzYUlymaeaewwGlJODO5SPkf1A4v21xLA1apGFOdcExvVJRmG8ruZ0aD8TD28nGbr7ycccWAXtHY=; 3:lz16F+GM8xgxtMd/+T5FIOWSNPahF+V9ipHPnP+usBp8nYQZzGieoG8rVVlO/+oWGqS1kY7A7GalHw+TLYPo2nVYQzghyvmqpsK+6uiROcr84wJAuIh9erktpse0Oh5qdVE7tk/oWRux5jlD7H0OBV4Mnfn50eYEeSFJ6o/o3kiU/iWV++PfJg0V6U/gNlWGG+jr7a8zNmIuAVI2ZzOvjraERToH4H17fSWufCSklWI=; 25:/VhiNwZgPKIF7Ej/hGFsDt+ppV+elmCxygVnwOki+zfKI3zHem6XIo0nfEGQE9ELEMs5dPma96A746dST8IKNCP0TEldMmiUfAM8S57aXseIaVLfjOXK0mfwijpegI18r/BToF4qN+nAe14ywQ3MCAg3+lD9AfWHZI6/dO5GdmHkfLtYxWF2cXLUhB+FvCw/M3Qxf7byJcLttmu4BAwDA92bjuFHhMM8YowIKfMpAZaYXFFUqRyqB3PQArlVSxjNrEqhUSnonAyqihuYcONmsQ==; 20:6NiTdJDdQDb8K6WtISeIC3LQUel6g2vaYC4omhLvD0lj3a3kF555nHsWiE3gWUJk/VMi1MwVYPTSRKcY+Fwj/wPo2drTQx1CfJjo62nIjAsB4ndxdyVg/ddi/mgzOIEP0XstdpAxywP9RbIp3Sm0h2vm6WeSoNh8/JxeMNPf6Xg= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1495; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(520078)(5005006)(8121501046)(3002001); SRVR:BN3PR03MB1495; BCL:0; PCL:0; RULEID:; SRVR:BN3PR03MB1495; X-Microsoft-Exchange-Diagnostics: 1; BN3PR03MB1495; 4:IDu2IxVN4YkoozgDrLASEfs7p1V1haXR27ECekMEj0l1cCob5U4DI3zumiO3/8y2EMG1k0YpNkJnRV1OUOcwqmYrbTjwoLaYn6Iy/dMQVM3T8Bt4yo8on8smPCZcfCNiomu5TWSB43NvPa/F66duncmFFsp+fqIbEcffJ1NvTqlgaDhyVYuI5no57iMicw1XUz6rFhV1KDGOc99MPYP2BJjPszwlhuhgPye4KsP5mvW6l49hGMfTM1z3HzgfsuntkigEOip+LW+uLMqbBKs1mN1HeVcIc5evbkHtLIV1UvHpQGsW+aKmhJ3UzNeU0zht5hL+YEjZNflNzI96RpfDug== X-Forefront-PRVS: 07063A0A30 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BN3PR03MB1495; 23:KSgbPlYhTus5haBzDHHkRFKh9UkguivvzztRMImOf?= =?us-ascii?Q?ngHgSnuhYVDgMxgcbgQZPPMQd/I4m2/yhU0IwXxJEweEfAR8x7tAKrNAojy0?= =?us-ascii?Q?3Vyw2vQ/kaP2HNii9/nxaa0jzYAzb/bxMekpjDQVgVkCma3lJNUrSd+iOU3P?= =?us-ascii?Q?ensC5LUIVeJkzVOc7D9VkUDCkzehKSnQlh/X07tC32UPWabc8XkRxYhP6iUQ?= =?us-ascii?Q?1o4ewgKtZVM8UCpzXHcwxaORVHKZafVZWkqtX86tiZwo0BlDMiBfd6QVUKER?= =?us-ascii?Q?r61XMtuUh8Sve2Mx7Yae6Gns7txAJBy5kSqlhQUoSVq/9KN7v7EyldiXXLNd?= =?us-ascii?Q?PTSQjRCARijiECNe7wRFAD9Km3uHWETHZT7Cum/5Yt4F6YlLgtOrY1JNfZUw?= =?us-ascii?Q?8e5oWI8VStAL02zDMWQbFnMdJ/DRnquZhFtJ/r7mLNMa3wUgMNtCz9SmEDWH?= =?us-ascii?Q?H0RvEkJESS6QaH7dD1kDwScf4yGIwGBgi2Ztib4vDXR4nyDs2Deh4M9rAblK?= =?us-ascii?Q?bXHjEbV0GHOpNe1o5JHX4TfiZQ00L/frQGORM6KfsFMjEI2cTuzPsrsD3Iy5?= =?us-ascii?Q?uJaJlmTzzcO4nybkiFfjC4CV1zzr1fNo1zsKCNViRipB+l0cPPYDM8mUm7kF?= =?us-ascii?Q?uWasq1pKdO910PDx08SM+Z1RPtL+/lvUqiNQqi6A01frNsMZrzf/LGGSRvui?= =?us-ascii?Q?KDgwpk1HxIG2GA7bp4K3i9ASIH5pJ9cIRmMrDyPCTuksxEa7nlIOiQVpbMs7?= =?us-ascii?Q?VAEZuM2l2cRWiI8gnH2gFuLKaUOpwMr8o3qN6inTmy2FI45P8jO7c7AaUfIg?= =?us-ascii?Q?3pxa8rTJpe/QfknW88BXXOnDYR0hAjc6C3Ierh/kGQKZX+aI8v2pgxbzbKtc?= =?us-ascii?Q?EwMxe1Cok++a9uEIBEKNkd78GPF29zxauwG8PsZ9RXOkMqJp11b8a+/ftrXa?= =?us-ascii?Q?ENBO5fvz0mT7wnVW6ovZWQLTf50F8uQiQkTAqxDjBha8ynJIeYGx3izCQHdx?= =?us-ascii?Q?xeFaTpUfMDm7F34vLrI5exybdKvgaREunETYymClY322nZqq9ImURP0+OXLJ?= =?us-ascii?Q?/RnEj+Xjgq7tCrckt5OtR/wZqnKP2rN09NCPF6HNr8waaCfvnL0uNqEbvNtl?= =?us-ascii?Q?upyyDVw+fv8igXrl35DRgNVY/7mxOFVkZU9ZKYKyVrhU29PoJ+KveAG1ROr7?= =?us-ascii?Q?fgusaPzPDRZPU8=3D?= X-Microsoft-Exchange-Diagnostics: 1; BN3PR03MB1495; 5:G91WK9M44cG6A4tfX/UJeLY47+EbtNH9qF4SKf8aUaNF4y/KOHwVDV4lWywRWau9kd+ac0KFg1/jccSxihkzH1A0fb+ELobSSIX74tsBJG+NjMq0VuE+T7uzBbgUm6S++NdYauMH/QJ7/OAq4WeNtw==; 24:QiWgD5pAiunabmglG7Q0cK9MdsNVmWSBf6zCV5zFlQnpj4UaJnK8kiwudlf6FQjdetRE4wsRC6y/b9GBrJpTQXbCuZl8/v8mbCmrNwsSbCA=; 20:Sy6d5RnSSgvkdk4hMhnQfNbOzgHeHZh8l/5R3iCxPUlwmZ5ws7KJscrXPrmsKZIR4AjQtSgsxSV2pOuTlaULfY/SPqCqqUQ8Aalrb9nrs/soaycaPaOW/nWuCsmjmBnKpGgxvGyDVoi+vRxdt2L8vjtrkIkEJC1UWyc4ay96/60= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Sep 2015 02:13:39.0472 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a; Ip=[66.35.236.227]; Helo=[sj-itexedge03.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB1495 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the Altera PCIe host controller driver. Signed-off-by: Ley Foon Tan Reviewed-by: Marc Zyngier --- drivers/pci/host/Kconfig | 8 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-altera.c | 591 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 600 insertions(+) create mode 100644 drivers/pci/host/pcie-altera.c diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index d5e58ba..df9ed4f 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -145,4 +145,12 @@ config PCIE_IPROC_BCMA Say Y here if you want to use the Broadcom iProc PCIe controller through the BCMA bus interface +config PCIE_ALTERA + tristate "Altera PCIe controller" + depends on ARCH_SOCFPGA || NIOS2 + select PCI_DOMAINS + help + Say Y here if you want to enable PCIe controller support for Altera + SoCFPGA family of SoCs. + endmenu diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index 140d66f..6954f76 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o +obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c new file mode 100644 index 0000000..41cd4fd --- /dev/null +++ b/drivers/pci/host/pcie-altera.c @@ -0,0 +1,591 @@ +/* + * Copyright Altera Corporation (C) 2013-2015. All rights reserved + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define A2P_ADDR_MAP_LO0 0x1000 +#define A2P_ADDR_MAP_HI0 0x1004 +#define RP_TX_REG0 0x2000 +#define RP_TX_REG1 0x2004 +#define RP_TX_CNTRL 0x2008 +#define RP_TX_EOP 0x2 +#define RP_TX_SOP 0x1 +#define RP_RXCPL_STATUS 0x2010 +#define RP_RXCPL_EOP 0x2 +#define RP_RXCPL_SOP 0x1 +#define RP_RXCPL_REG0 0x2014 +#define RP_RXCPL_REG1 0x2018 +#define P2A_INT_STATUS 0x3060 +#define P2A_INT_STS_ALL 0xF +#define P2A_INT_ENABLE 0x3070 +#define P2A_INT_ENA_ALL 0xF +#define RP_LTSSM 0x3C64 +#define LTSSM_L0 0xF + +/* TLP configuration type 0 and 1 */ +#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */ +#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */ +#define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */ +#define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */ +#define TLP_PAYLOAD_SIZE 0x01 +#define TLP_READ_TAG 0x1D +#define TLP_WRITE_TAG 0x10 +#define TLP_CFG_DW0(fmttype) (((fmttype) << 24) | TLP_PAYLOAD_SIZE) +#define TLP_CFG_DW1(reqid, tag) (((reqid) << 16) | (tag << 8) | 0xF) +#define TLP_CFG_DW2(bus, devfn, offset) \ + (((bus) << 24) | ((devfn) << 16) | (offset)) +#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) +#define TLP_COMPL_STATUS(hdr) (((hdr) & 0xE0) >> 13) +#define TLP_HDR_SIZE 3 +#define TLP_LOOP 500 + +#define INTX_NUM 4 + +#define DWORD_MASK 3 + +struct altera_pcie { + struct platform_device *pdev; + void __iomem *cra_base; + int irq; + u8 root_bus_nr; + struct irq_domain *irq_domain; + struct resource bus_range; + struct list_head resources; +}; + +struct tlp_rp_regpair_t { + u32 ctrl; + u32 reg0; + u32 reg1; +}; + +static void altera_pcie_retrain(struct pci_dev *dev) +{ + u16 linkcap, linkstat; + + /* + * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but + * current speed is 2.5 GB/s. + */ + pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap); + + if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) + return; + + pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat); + if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) + pcie_capability_set_word(dev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_RL); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ALTERA, PCI_ANY_ID, altera_pcie_retrain); + +static void altera_pcie_fixup_res(struct pci_dev *dev) +{ + /* + * Prevent enumeration of root port. + */ + if (!dev->bus->parent && dev->devfn == 0) { + int i; + + for (i = 0; i < PCI_NUM_RESOURCES; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ALTERA, PCI_ANY_ID, + altera_pcie_fixup_res); + +static inline void cra_writel(struct altera_pcie *pcie, u32 value, u32 reg) +{ + writel_relaxed(value, pcie->cra_base + reg); +} + +static inline u32 cra_readl(struct altera_pcie *pcie, u32 reg) +{ + return readl_relaxed(pcie->cra_base + reg); +} + +static void tlp_read_rx(struct altera_pcie *pcie, + struct tlp_rp_regpair_t *tlp_rp_regdata) +{ + tlp_rp_regdata->ctrl = cra_readl(pcie, RP_RXCPL_STATUS); + tlp_rp_regdata->reg0 = cra_readl(pcie, RP_RXCPL_REG0); + tlp_rp_regdata->reg1 = cra_readl(pcie, RP_RXCPL_REG1); +} + +static void tlp_write_tx(struct altera_pcie *pcie, + struct tlp_rp_regpair_t *tlp_rp_regdata) +{ + cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0); + cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1); + cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL); +} + +static bool altera_pcie_link_is_up(struct altera_pcie *pcie) +{ + return !!(cra_readl(pcie, RP_LTSSM) & LTSSM_L0); +} + +static bool altera_pcie_valid_config(struct altera_pcie *pcie, + struct pci_bus *bus, int dev) +{ + /* If there is no link, then there is no device */ + if (bus->number != pcie->root_bus_nr) { + if (!altera_pcie_link_is_up(pcie)) + return false; + } + + /* access only one slot on each root port */ + if (bus->number == pcie->root_bus_nr && dev > 0) + return false; + + /* + * Do not read more than one device on the bus directly attached + * to root port, root port can only attach to one downstream port. + */ + if (bus->primary == pcie->root_bus_nr && dev > 0) + return false; + + return true; +} + +static int tlp_read_packet(struct altera_pcie *pcie, u32 *value) +{ + u8 loop; + struct tlp_rp_regpair_t tlp_rp_regdata; + + /* + * Minimum 2 loops to read TLP headers and 1 loop to read data + * payload. + */ + for (loop = 0; loop < TLP_LOOP; loop++) { + tlp_read_rx(pcie, &tlp_rp_regdata); + if (tlp_rp_regdata.ctrl & RP_RXCPL_EOP) { + if (value) + *value = tlp_rp_regdata.reg0; + return PCIBIOS_SUCCESSFUL; + } + udelay(5); + } + + return -ENOENT; +} + +static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers, + u32 data, bool align) +{ + struct tlp_rp_regpair_t tlp_rp_regdata; + + tlp_rp_regdata.reg0 = headers[0]; + tlp_rp_regdata.reg1 = headers[1]; + tlp_rp_regdata.ctrl = RP_TX_SOP; + tlp_write_tx(pcie, &tlp_rp_regdata); + + if (align) { + tlp_rp_regdata.reg0 = headers[2]; + tlp_rp_regdata.reg1 = 0; + tlp_rp_regdata.ctrl = 0; + tlp_write_tx(pcie, &tlp_rp_regdata); + + tlp_rp_regdata.reg0 = data; + tlp_rp_regdata.reg1 = 0; + } else { + tlp_rp_regdata.reg0 = headers[2]; + tlp_rp_regdata.reg1 = data; + } + + tlp_rp_regdata.ctrl = RP_TX_EOP; + tlp_write_tx(pcie, &tlp_rp_regdata); +} + +static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn, + int where, u32 *value) +{ + int ret; + u32 headers[TLP_HDR_SIZE]; + + if (bus == pcie->root_bus_nr) + headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0); + else + headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1); + + headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, devfn), + TLP_READ_TAG); + headers[2] = TLP_CFG_DW2(bus, devfn, where); + + tlp_write_packet(pcie, headers, 0, false); + + ret = tlp_read_packet(pcie, value); + if (ret != PCIBIOS_SUCCESSFUL) + *value = ~0UL; /* return 0xFFFFFFFF if error */ + + return ret; +} + +static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn, + int where, u32 value) +{ + u32 headers[TLP_HDR_SIZE]; + int ret; + + if (bus == pcie->root_bus_nr) + headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0); + else + headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1); + + headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, devfn), + TLP_WRITE_TAG); + headers[2] = TLP_CFG_DW2(bus, devfn, where); + + /* check alignment to Qword */ + if ((where & 0x7) == 0) + tlp_write_packet(pcie, headers, value, true); + else + tlp_write_packet(pcie, headers, value, false); + + ret = tlp_read_packet(pcie, NULL); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + + /* + * Monitoring changes to PCI_PRIMARY_BUS register on root port and update + * local copy of root bus number accordingly. + */ + if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS)) + pcie->root_bus_nr = (u8)(value); + + return PCIBIOS_SUCCESSFUL; +} + +static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + struct altera_pcie *pcie = bus->sysdata; + int ret; + u32 data; + + if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) { + *value = ~0UL; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + ret = tlp_cfg_dword_read(pcie, bus->number, devfn, + (where & ~DWORD_MASK), &data); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + + switch (size) { + case 1: + *value = (data >> (8 * (where & 0x3))) & 0xff; + break; + case 2: + *value = (data >> (8 * (where & 0x2))) & 0xffff; + break; + default: + *value = data; + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + struct altera_pcie *pcie = bus->sysdata; + u32 data32; + u32 shift = 8 * (where & 3); + int ret; + + if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* write partial */ + if (size != sizeof(u32)) { + ret = tlp_cfg_dword_read(pcie, bus->number, devfn, + where & ~DWORD_MASK, &data32); + if (ret) + return ret; + } + + switch (size) { + case 1: + data32 = (data32 & ~(0xff << shift)) | + ((value & 0xff) << shift); + break; + case 2: + data32 = (data32 & ~(0xffff << shift)) | + ((value & 0xffff) << shift); + break; + default: + data32 = value; + break; + } + + return tlp_cfg_dword_write(pcie, bus->number, devfn, + (where & ~DWORD_MASK), data32); +} + +static struct pci_ops altera_pcie_ops = { + .read = altera_pcie_cfg_read, + .write = altera_pcie_cfg_write, +}; + +static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops = { + .map = altera_pcie_intx_map, +}; + +static void altera_pcie_isr(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct altera_pcie *pcie; + unsigned long status; + u32 bit; + u32 virq; + + chained_irq_enter(chip, desc); + pcie = irq_desc_get_handler_data(desc); + + while ((status = cra_readl(pcie, P2A_INT_STATUS) + & P2A_INT_STS_ALL) != 0) { + for_each_set_bit(bit, &status, INTX_NUM) { + /* clear interrupts */ + cra_writel(pcie, 1 << bit, P2A_INT_STATUS); + + virq = irq_find_mapping(pcie->irq_domain, bit + 1); + if (virq) + generic_handle_irq(virq); + else + dev_err(&pcie->pdev->dev, "unexpected IRQ\n"); + } + } + + chained_irq_exit(chip, desc); +} + +static void altera_pcie_release_of_pci_ranges(struct altera_pcie *pcie) +{ + pci_free_resource_list(&pcie->resources); +} + +static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie) +{ + int err, res_valid = 0; + struct device *dev = &pcie->pdev->dev; + struct device_node *np = dev->of_node; + struct resource_entry *win; + + err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources, + NULL); + if (err) + return err; + + resource_list_for_each_entry(win, &pcie->resources) { + struct resource *parent, *res = win->res; + + switch (resource_type(res)) { + case IORESOURCE_MEM: + parent = &iomem_resource; + res_valid |= !(res->flags & IORESOURCE_PREFETCH); + break; + default: + continue; + } + + err = devm_request_resource(dev, parent, res); + if (err) + goto out_release_res; + } + + if (!res_valid) { + dev_err(dev, "non-prefetchable memory resource required\n"); + err = -EINVAL; + goto out_release_res; + } + + return 0; + +out_release_res: + altera_pcie_release_of_pci_ranges(pcie); + return err; +} + +static void altera_pcie_free_irq_domain(struct altera_pcie *pcie) +{ + int i; + u32 irq; + + for (i = 0; i < INTX_NUM; i++) { + irq = irq_find_mapping(pcie->irq_domain, i + 1); + if (irq > 0) + irq_dispose_mapping(irq); + } + + irq_domain_remove(pcie->irq_domain); +} + +static int altera_pcie_init_irq_domain(struct altera_pcie *pcie) +{ + struct device *dev = &pcie->pdev->dev; + struct device_node *node = dev->of_node; + + /* Setup INTx */ + pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM, + &intx_domain_ops, pcie); + if (!pcie->irq_domain) { + dev_err(dev, "Failed to get a INTx IRQ domain\n"); + return -ENOMEM; + } + + return 0; +} + +static int altera_pcie_parse_dt(struct altera_pcie *pcie) +{ + struct resource *cra; + struct platform_device *pdev = pcie->pdev; + + cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra"); + if (!cra) { + cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cra"); + if (!cra) { + dev_err(&pdev->dev, + "no cra memory resource defined\n"); + return -ENODEV; + } + } + + pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra); + if (IS_ERR(pcie->cra_base)) { + dev_err(&pdev->dev, "failed to map cra memory\n"); + return PTR_ERR(pcie->cra_base); + } + + /* setup IRQ */ + pcie->irq = platform_get_irq(pdev, 0); + if (pcie->irq <= 0) { + dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq); + return -EINVAL; + } + + irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie); + + return 0; +} + +static int altera_pcie_probe(struct platform_device *pdev) +{ + struct altera_pcie *pcie; + struct pci_bus *bus; + struct pci_bus *child; + int ret; + + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->pdev = pdev; + + ret = altera_pcie_parse_dt(pcie); + if (ret) { + dev_err(&pdev->dev, "Parsing DT failed\n"); + return ret; + } + + INIT_LIST_HEAD(&pcie->resources); + + ret = altera_pcie_parse_request_of_pci_ranges(pcie); + if (ret) { + dev_err(&pdev->dev, "Failed add resources\n"); + return ret; + } + + ret = altera_pcie_init_irq_domain(pcie); + if (ret) { + dev_err(&pdev->dev, "Failed creating IRQ Domain\n"); + return ret; + } + + /* clear all interrupts */ + cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS); + /* enable all interrupts */ + cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE); + + bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops, + pcie, &pcie->resources); + if (!bus) + return -ENOMEM; + + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); + pci_assign_unassigned_bus_resources(bus); + pci_bus_add_devices(bus); + + /* Configure PCI Express setting. */ + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + + platform_set_drvdata(pdev, pcie); + return ret; +} + +static int altera_pcie_remove(struct platform_device *pdev) +{ + struct altera_pcie *pcie = platform_get_drvdata(pdev); + + altera_pcie_free_irq_domain(pcie); + platform_set_drvdata(pdev, NULL); + return 0; +} + +static const struct of_device_id altera_pcie_of_match[] = { + { .compatible = "altr,pcie-root-port-1.0", }, + {}, +}; +MODULE_DEVICE_TABLE(of, altera_pcie_of_match); + +static struct platform_driver altera_pcie_driver = { + .probe = altera_pcie_probe, + .remove = altera_pcie_remove, + .driver = { + .name = "altera-pcie", + .of_match_table = altera_pcie_of_match, + }, +}; + +module_platform_driver(altera_pcie_driver); + +MODULE_AUTHOR("Ley Foon Tan "); +MODULE_DESCRIPTION("Altera PCIe host controller driver"); +MODULE_LICENSE("GPL v2");