From patchwork Tue Sep 29 11:34:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 7285391 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 244B7BF90C for ; Tue, 29 Sep 2015 11:27:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4668F206ED for ; Tue, 29 Sep 2015 11:27:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 46238206E1 for ; Tue, 29 Sep 2015 11:27:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964842AbbI2L1n (ORCPT ); Tue, 29 Sep 2015 07:27:43 -0400 Received: from szxga01-in.huawei.com ([58.251.152.64]:47449 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964843AbbI2L1b (ORCPT ); Tue, 29 Sep 2015 07:27:31 -0400 Received: from 172.24.1.50 (EHLO SZXEML424-HUB.china.huawei.com) ([172.24.1.50]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CVZ43149; Tue, 29 Sep 2015 19:27:28 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by SZXEML424-HUB.china.huawei.com (10.82.67.153) with Microsoft SMTP Server id 14.3.235.1; Tue, 29 Sep 2015 19:27:18 +0800 From: Gabriele Paoloni To: , , CC: , , , , , , , Subject: [PATCH v4 1/3] PCIE: spear13xx: fix addresses in dw_pcie_cfg_read and dw_pcie_cfg_write Date: Tue, 29 Sep 2015 19:34:05 +0800 Message-ID: <1443526447-228817-2-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1443526447-228817-1-git-send-email-gabriele.paoloni@huawei.com> References: <1443526447-228817-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: gabriele paoloni Currently spear13xx passes the wrong "address" in many calls to dw_pcie_cfg_read and dw_pcie_cfg_write: the passed address is always pp->dbi_base, that is wrong as it does not consider the offset to access the right register of the PCI header. This patches fixes these function calls passing the address to access the right register. Signed-off-by: Gabriele Paoloni --- drivers/pci/host/pcie-spear13xx.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c index 98d2683..a5997e3 100644 --- a/drivers/pci/host/pcie-spear13xx.c +++ b/drivers/pci/host/pcie-spear13xx.c @@ -146,6 +146,7 @@ struct pcie_app_reg { static int spear13xx_pcie_establish_link(struct pcie_port *pp) { u32 val; + int where; struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp); struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; u32 exp_cap_off = EXP_CAP_ID_OFFSET; @@ -163,9 +164,10 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp) * default value in capability register is 512 bytes. So force * it to 128 here. */ - dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val); + where = exp_cap_off + PCI_EXP_DEVCTL; + dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 4, &val); val &= ~PCI_EXP_DEVCTL_READRQ; - dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val); + dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, 4, val); dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A); dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80); @@ -175,22 +177,24 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp) * also works */ if (spear13xx_pcie->is_gen1) { - dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4, + where = exp_cap_off + PCI_EXP_LNKCAP; + dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 4, &val); if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + - PCI_EXP_LNKCAP, 4, val); + dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), + where, 4, val); } - dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4, + where = exp_cap_off + PCI_EXP_LNKCTL2; + dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 4, &val); if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + - PCI_EXP_LNKCTL2, 4, val); + dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), + where, 4, val); } }