From patchwork Sat Oct 3 21:11:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 7322621 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2912FBEEA4 for ; Sat, 3 Oct 2015 21:12:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2B49920795 for ; Sat, 3 Oct 2015 21:12:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1129320794 for ; Sat, 3 Oct 2015 21:12:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750883AbbJCVMA (ORCPT ); Sat, 3 Oct 2015 17:12:00 -0400 Received: from mail-qg0-f48.google.com ([209.85.192.48]:33340 "EHLO mail-qg0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750788AbbJCVL7 (ORCPT ); Sat, 3 Oct 2015 17:11:59 -0400 Received: by qgev79 with SMTP id v79so121362914qge.0 for ; Sat, 03 Oct 2015 14:11:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=zUi8XfFBmEllXFn0+zxaQWvjSJEvZ81gdJ4eTXhTYQc=; b=E7dlOuIJ6vuP6EzRyMAZ+1K669WVCARwE8zwcgkaKY+IvEjlCgyQqF2f5vDc8iwdg+ vn9002U48Sm4oSlxjKy1fiZwsG48KfAzDmJ5X8Tg/9fXa0hm/E6VRuZtQw985QhCaev6 aBNS4wxfqmA1C4MO7xICg/bAG5j8EuIYd+bPTsZhZwmb+blu+xMHhjvtaaUHbj1N4Cno WaDBOb0bcgUycdoJHOaFxmFaN1JgMmoFL0Q5er8lSbISQtRiSp82d6Wi4zkJhCy9rivq SOAYlSP3mwqP4MYa73BkjtQoScbUi5mJyYYhPG4eyqIMqfW1QVU01NWlLa//rOs24y/M ZbAw== X-Received: by 10.140.96.200 with SMTP id k66mr28859665qge.81.1443906718887; Sat, 03 Oct 2015 14:11:58 -0700 (PDT) Received: from localhost.localdomain ([189.5.19.77]) by smtp.gmail.com with ESMTPSA id d9sm7591086qka.49.2015.10.03.14.11.55 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 03 Oct 2015 14:11:57 -0700 (PDT) From: Fabio Estevam To: bhelgaas@google.com Cc: pratyush.anand@gmail.com, l.stach@pengutronix.de, linux-pci@vger.kernel.org, Fabio Estevam Subject: [PATCH 1/2] PCI: spear: Move LTSSM state definitions to pcie-designware.h Date: Sat, 3 Oct 2015 18:11:30 -0300 Message-Id: <1443906691-14642-1-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY,UPPERCASE_50_75 autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Fabio Estevam Move LTSSM state definitions to common pcie-designware.h so that other drivers can make use of them. Signed-off-by: Fabio Estevam Acked-by: Pratyush Anand --- drivers/pci/host/pcie-designware.h | 34 ++++++++++++++++++++++++++++++++++ drivers/pci/host/pcie-spear13xx.c | 33 --------------------------------- 2 files changed, 34 insertions(+), 33 deletions(-) diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 35123d9..97d6558 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -22,6 +22,40 @@ #define MAX_MSI_IRQS 32 #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) +#define LTSSM_STATE_DETECT_QUIET 0x00 +#define LTSSM_STATE_DETECT_ACT 0x01 +#define LTSSM_STATE_POLL_ACTIVE 0x02 +#define LTSSM_STATE_POLL_COMPLIANCE 0x03 +#define LTSSM_STATE_POLL_CONFIG 0x04 +#define LTSSM_STATE_PRE_DETECT_QUIET 0x05 +#define LTSSM_STATE_DETECT_WAIT 0x06 +#define LTSSM_STATE_CFG_LINKWD_START 0x07 +#define LTSSM_STATE_CFG_LINKWD_ACEPT 0x08 +#define LTSSM_STATE_CFG_LANENUM_WAIT 0x09 +#define LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A +#define LTSSM_STATE_CFG_COMPLETE 0x0B +#define LTSSM_STATE_CFG_IDLE 0x0C +#define LTSSM_STATE_RCVRY_LOCK 0x0D +#define LTSSM_STATE_RCVRY_SPEED 0x0E +#define LTSSM_STATE_RCVRY_RCVRCFG 0x0F +#define LTSSM_STATE_RCVRY_IDLE 0x10 +#define LTSSM_STATE_L0 0x11 +#define LTSSM_STATE_L0S 0x12 +#define LTSSM_STATE_L123_SEND_EIDLE 0x13 +#define LTSSM_STATE_L1_IDLE 0x14 +#define LTSSM_STATE_L2_IDLE 0x15 +#define LTSSM_STATE_L2_WAKE 0x16 +#define LTSSM_STATE_DISABLED_ENTRY 0x17 +#define LTSSM_STATE_DISABLED_IDLE 0x18 +#define LTSSM_STATE_DISABLED 0x19 +#define LTSSM_STATE_LPBK_ENTRY 0x1A +#define LTSSM_STATE_LPBK_ACTIVE 0x1B +#define LTSSM_STATE_LPBK_EXIT 0x1C +#define LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D +#define LTSSM_STATE_HOT_RESET_ENTRY 0x1E +#define LTSSM_STATE_HOT_RESET 0x1F +#define LTSSM_STATE_MASK 0x3F + struct pcie_port { struct device *dev; u8 root_bus_nr; diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c index 98d2683..920d399 100644 --- a/drivers/pci/host/pcie-spear13xx.c +++ b/drivers/pci/host/pcie-spear13xx.c @@ -84,39 +84,6 @@ struct pcie_app_reg { #define APPS_PM_XMT_PME_ID 5 /* CR3 ID */ -#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00 -#define XMLH_LTSSM_STATE_DETECT_ACT 0x01 -#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02 -#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03 -#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04 -#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05 -#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06 -#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07 -#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08 -#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09 -#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A -#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B -#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C -#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D -#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E -#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F -#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10 -#define XMLH_LTSSM_STATE_L0 0x11 -#define XMLH_LTSSM_STATE_L0S 0x12 -#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13 -#define XMLH_LTSSM_STATE_L1_IDLE 0x14 -#define XMLH_LTSSM_STATE_L2_IDLE 0x15 -#define XMLH_LTSSM_STATE_L2_WAKE 0x16 -#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17 -#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18 -#define XMLH_LTSSM_STATE_DISABLED 0x19 -#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A -#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B -#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C -#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D -#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E -#define XMLH_LTSSM_STATE_HOT_RESET 0x1F -#define XMLH_LTSSM_STATE_MASK 0x3F #define XMLH_LINK_UP (1 << 6) /* CR4 ID */