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Sat, 10 Oct 2015 06:22:54 +0000 Received: from lmh.ap.freescale.net (lmh.ap.freescale.net [10.193.20.20]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t9A6MlFP002625; Fri, 9 Oct 2015 23:22:48 -0700 From: Minghuan Lian To: CC: , Zang Roy-R61911 , Hu Mingkai-B21284 , "Yoder Stuart-B08248" , Li Yang , Arnd Bergmann , Bjorn Helgaas , "Jingoo Han" , Zhou Wang , "Minghuan Lian" Subject: [PATCH v3] PCI: layerscape: Add PCIe support for LS1043a and LS2080a Date: Sat, 10 Oct 2015 14:23:37 +0800 Message-ID: <1444458217-31004-1-git-send-email-Minghuan.Lian@freescale.com> X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11OLC009; 1:XhPVYfF962EjJMv2TNnhFJQ8d7EJicZcT+V/J9c3khHbQTwrJQHjXZu4QdA18IhuZi0vNMf7wIuNdgLEB0u5kuHwuLS2y0uw0UamhEQT8Sw5JGC7jOl7maroTVJZ+KqiRYjxVq/2H+H+oCNXjv93mjpWJZKsgjkUGNvh/JL03acAJwDhzr9nX1NmfonEbz0h6M6iXi3YZ6gCEZ8mEpla36UH+e/Qf/YFG8z9UNNSyIJJ4xZi4hCsg5BxUn7eG6sHMoCgSf2CZAtCXBtu7eT38ILM4+VRtq4qYWhognYVmqwmqA6i4+m6Gjb0g3+7ZS9UB5sK7DtJZRJ5kmdiw2aOhjF/2GdRziz+/Pn5pSWsN6Iwmw6U1+HAtlHqd2s8H84wbqIsmcIClGDdEg12zJcc2A== X-Forefront-Antispam-Report: CIP:192.88.158.2; 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DM2PR0301MB1263; 5:e9/vwTAxFS0yZm2emTRR7a6hnowJgopdQ61B+0QT1bsZmUXmo6NV9Qo306K1Liw0fXzi526UALZfW+3i21X5f3FRHpB/J6Ozw0M9MTuU2NbmX2Om2L35GJf7s13fnMidaRUQq7pDfeyiztPdVS21YA==; 24:LhMHhK2cyC7kn+ZQ+AJY6h/aC3K1CHVXbBUdCfKaN0IT1d5URLwnWQ82/FK/N4s/yqk6lmXLVzZJI4RxAc9dpb4QKGrYwK6JXM+qjma+WDQ=; 20:HBR5wq/8QOrWZr+SjULuFSv+XvdR4oPE4i4B0ellzfUeul/egFhBG+wnematRmkyf8hzSoXusGvb66K1AUqVlQ== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2015 06:22:54.7601 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0301MB1263 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds PCIe support for LS1043a and LS2080a. Signed-off-by: Minghuan Lian --- This patch is based on v4.3-rc4 and [PATCH v10 3/6] PCI: designware: Add ARM64 support. change log v3: 1. Use 8 or 16 bit access function to simplify code 2. Add ls_add_pcie_port in accordance with other DesignWare-based drivers v2: 1. Rename ls2085a to ls2080a 2. Add ls_pcie_msi_host_init() drivers/pci/host/Kconfig | 2 +- drivers/pci/host/pci-layerscape.c | 215 +++++++++++++++++++++++++++----------- 2 files changed, 153 insertions(+), 64 deletions(-) diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index d5e58ba..b5f1a3b 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -105,7 +105,7 @@ config PCI_XGENE_MSI config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" - depends on OF && ARM + depends on OF && (ARM || ARM64) select PCIE_DW select MFD_SYSCON help diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index b2328ea1..024727f 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -11,7 +11,6 @@ */ #include -#include #include #include #include @@ -32,27 +31,60 @@ #define LTSSM_STATE_MASK 0x3f #define LTSSM_PCIE_L0 0x11 /* L0 state */ -/* Symbol Timer Register and Filter Mask Register 1 */ -#define PCIE_STRFMR1 0x71c +/* PEX Internal Configuration Registers */ +#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ +#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ + +/* PEX LUT registers */ +#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */ + +struct ls_pcie_drvdata { + u32 lut_offset; + u32 ltssm_shift; + struct pcie_host_ops *ops; +}; struct ls_pcie { - struct list_head node; - struct device *dev; - struct pci_bus *bus; - void __iomem *dbi; - struct regmap *scfg; struct pcie_port pp; + const struct ls_pcie_drvdata *drvdata; + void __iomem *regs; + void __iomem *lut; + struct regmap *scfg; int index; - int msi_irq; }; #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) -static int ls_pcie_link_up(struct pcie_port *pp) +static bool ls_pcie_is_bridge(struct ls_pcie *pcie) +{ + u32 header_type; + + header_type = ioread8(pcie->regs + PCI_HEADER_TYPE); + header_type &= 0x7f; + + return header_type == PCI_HEADER_TYPE_BRIDGE; +} + +/* Clear multi-function bit */ +static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) +{ + iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->regs + PCI_HEADER_TYPE); +} + +/* Fix class value */ +static void ls_pcie_fix_class(struct ls_pcie *pcie) +{ + iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->regs + PCI_CLASS_DEVICE); +} + +static int ls1021_pcie_link_up(struct pcie_port *pp) { u32 state; struct ls_pcie *pcie = to_ls_pcie(pp); + if (!pcie->scfg) + return 0; + regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state); state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; @@ -62,56 +94,124 @@ static int ls_pcie_link_up(struct pcie_port *pp) return 1; } -static int ls_pcie_establish_link(struct pcie_port *pp) +static void ls1021_pcie_host_init(struct pcie_port *pp) { - unsigned int retries; + struct ls_pcie *pcie = to_ls_pcie(pp); + u32 val, index[2]; - for (retries = 0; retries < 200; retries++) { - if (dw_pcie_link_up(pp)) - return 0; - usleep_range(100, 1000); + pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node, + "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + dev_err(pp->dev, "No syscfg phandle specified\n"); + pcie->scfg = NULL; + return; } - dev_err(pp->dev, "phy link never came up\n"); - return -EINVAL; + if (of_property_read_u32_array(pp->dev->of_node, + "fsl,pcie-scfg", index, 2)) { + pcie->scfg = NULL; + return; + } + pcie->index = index[1]; + + /* + * LS1021A Workaround for internal TKT228622 + * to fix the INTx hang issue + */ + val = ioread32(pcie->regs + PCIE_STRFMR1); + val &= 0xffff; + iowrite32(val, pcie->regs + PCIE_STRFMR1); +} + +static int ls_pcie_link_up(struct pcie_port *pp) +{ + struct ls_pcie *pcie = to_ls_pcie(pp); + u32 state; + + state = (ioread32(pcie->lut + PCIE_LUT_DBG) >> + pcie->drvdata->ltssm_shift) & + LTSSM_STATE_MASK; + + if (state < LTSSM_PCIE_L0) + return 0; + + return 1; } static void ls_pcie_host_init(struct pcie_port *pp) { struct ls_pcie *pcie = to_ls_pcie(pp); - u32 val; - dw_pcie_setup_rc(pp); - ls_pcie_establish_link(pp); + iowrite32(1, pcie->regs + PCIE_DBI_RO_WR_EN); + ls_pcie_fix_class(pcie); + ls_pcie_clear_multifunction(pcie); + iowrite32(0, pcie->regs + PCIE_DBI_RO_WR_EN); +} - /* - * LS1021A Workaround for internal TKT228622 - * to fix the INTx hang issue - */ - val = ioread32(pcie->dbi + PCIE_STRFMR1); - val &= 0xffff; - iowrite32(val, pcie->dbi + PCIE_STRFMR1); +static int ls_pcie_msi_host_init(struct pcie_port *pp, + struct msi_controller *chip) +{ + struct device_node *msi_node; + struct device_node *np = pp->dev->of_node; + + msi_node = of_parse_phandle(np, "msi-parent", 0); + if (!msi_node) { + dev_err(pp->dev, "failed to find msi-parent\n"); + return -EINVAL; + } + + return 0; } +static struct pcie_host_ops ls1021_pcie_host_ops = { + .link_up = ls1021_pcie_link_up, + .host_init = ls1021_pcie_host_init, + .msi_host_init = ls_pcie_msi_host_init, +}; + static struct pcie_host_ops ls_pcie_host_ops = { .link_up = ls_pcie_link_up, .host_init = ls_pcie_host_init, + .msi_host_init = ls_pcie_msi_host_init, +}; + +static struct ls_pcie_drvdata ls1021_drvdata = { + .ops = &ls1021_pcie_host_ops, +}; + +static struct ls_pcie_drvdata ls1043_drvdata = { + .lut_offset = 0x10000, + .ltssm_shift = 24, + .ops = &ls_pcie_host_ops, +}; + +static struct ls_pcie_drvdata ls2080_drvdata = { + .lut_offset = 0x80000, + .ltssm_shift = 0, + .ops = &ls_pcie_host_ops, }; -static int ls_add_pcie_port(struct ls_pcie *pcie) +static const struct of_device_id ls_pcie_of_match[] = { + { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, + { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, + { }, +}; +MODULE_DEVICE_TABLE(of, ls_pcie_of_match); + +static int __init ls_add_pcie_port(struct pcie_port *pp, + struct platform_device *pdev) { - struct pcie_port *pp; int ret; + struct ls_pcie *pcie = to_ls_pcie(pp); - pp = &pcie->pp; - pp->dev = pcie->dev; - pp->dbi_base = pcie->dbi; - pp->root_bus_nr = -1; - pp->ops = &ls_pcie_host_ops; + pp->dev = &pdev->dev; + pp->dbi_base = pcie->regs; + pp->ops = pcie->drvdata->ops; ret = dw_pcie_host_init(pp); if (ret) { - dev_err(pp->dev, "failed to initialize host\n"); + dev_err(&pdev->dev, "failed to initialize host\n"); return ret; } @@ -120,39 +220,34 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) static int __init ls_pcie_probe(struct platform_device *pdev) { + const struct of_device_id *match; struct ls_pcie *pcie; - struct resource *dbi_base; - u32 index[2]; + struct resource *res; int ret; + match = of_match_device(ls_pcie_of_match, &pdev->dev); + if (!match) + return -ENODEV; + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; - pcie->dev = &pdev->dev; - - dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); - pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base); - if (IS_ERR(pcie->dbi)) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); + pcie->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pcie->regs)) { dev_err(&pdev->dev, "missing *regs* space\n"); - return PTR_ERR(pcie->dbi); + return PTR_ERR(pcie->regs); } - pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "fsl,pcie-scfg"); - if (IS_ERR(pcie->scfg)) { - dev_err(&pdev->dev, "No syscfg phandle specified\n"); - return PTR_ERR(pcie->scfg); - } + pcie->drvdata = match->data; + pcie->lut = pcie->regs + pcie->drvdata->lut_offset; - ret = of_property_read_u32_array(pdev->dev.of_node, - "fsl,pcie-scfg", index, 2); - if (ret) - return ret; - pcie->index = index[1]; + if (!ls_pcie_is_bridge(pcie)) + return -ENODEV; - ret = ls_add_pcie_port(pcie); - if (ret < 0) + ret = ls_add_pcie_port(&pcie->pp, pdev); + if (ret) return ret; platform_set_drvdata(pdev, pcie); @@ -160,12 +255,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id ls_pcie_of_match[] = { - { .compatible = "fsl,ls1021a-pcie" }, - { }, -}; -MODULE_DEVICE_TABLE(of, ls_pcie_of_match); - static struct platform_driver ls_pcie_driver = { .driver = { .name = "layerscape-pcie",