From patchwork Wed Feb 3 11:30:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 8201381 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E0148BEEE5 for ; Wed, 3 Feb 2016 11:50:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 02F1120266 for ; Wed, 3 Feb 2016 11:50:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1534E201ED for ; Wed, 3 Feb 2016 11:50:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755897AbcBCLcI (ORCPT ); Wed, 3 Feb 2016 06:32:08 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:63510 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755528AbcBCLcG (ORCPT ); Wed, 3 Feb 2016 06:32:06 -0500 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 7C5F5D0B2844; Wed, 3 Feb 2016 11:32:01 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 3 Feb 2016 11:32:03 +0000 Received: from localhost (10.100.200.105) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Wed, 3 Feb 2016 11:32:03 +0000 From: Paul Burton To: , Ralf Baechle CC: Paul Burton , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Michal Simek , "Jiang Liu" , Grygorii Strashko , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , , Russell Joyce , , Thomas Gleixner , "Jingoo Han" , Subject: [PATCH v2 04/15] PCI: xilinx: Keep references to both IRQ domains Date: Wed, 3 Feb 2016 11:30:34 +0000 Message-ID: <1454499045-5020-5-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> References: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.105] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP pcie-xilinx creates 2 IRQ domains when built with MSI support: one for MSI interrupts & one for legacy INTx interrupts. However, it only kept a reference to the MSI IRQ domain. This means that any INTx interrupts that may occur would be mapped using the wrong domain, and that only the MSI IRQ domain would be removed along with the driver. Track both IRQ domains & clean up both as appropriate. Signed-off-by: Paul Burton Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver") --- Changes in v2: - Add Fixes tag. drivers/pci/host/pcie-xilinx.c | 58 ++++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 4cfa463..1490bd1 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -105,6 +105,7 @@ * @root_busno: Root Bus number * @dev: Device pointer * @irq_domain: IRQ domain pointer + * @msi_irq_domain: MSI IRQ domain pointer * @bus_range: Bus range * @resources: Bus Resources */ @@ -115,6 +116,7 @@ struct xilinx_pcie_port { u8 root_busno; struct device *dev; struct irq_domain *irq_domain; + struct irq_domain *msi_irq_domain; struct resource bus_range; struct list_head resources; }; @@ -291,7 +293,7 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip, if (hwirq < 0) return hwirq; - irq = irq_create_mapping(port->irq_domain, hwirq); + irq = irq_create_mapping(port->msi_irq_domain, hwirq); if (!irq) return -EINVAL; @@ -517,31 +519,21 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) /** * xilinx_pcie_free_irq_domain - Free IRQ domain - * @port: PCIe port information + * @domain: the IRQ domain to free + * @nr: the number of IRQs in the domain */ -static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port) +static void xilinx_pcie_free_irq_domain(struct irq_domain *domain, int nr) { int i; - u32 irq, num_irqs; - - /* Free IRQ Domain */ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - - free_pages(port->msi_pages, 0); - - num_irqs = XILINX_NUM_MSI_IRQS; - } else { - /* INTx */ - num_irqs = 4; - } + u32 irq; - for (i = 0; i < num_irqs; i++) { - irq = irq_find_mapping(port->irq_domain, i); + for (i = 0; i < nr; i++) { + irq = irq_find_mapping(domain, i); if (irq > 0) irq_dispose_mapping(irq); } - irq_domain_remove(port->irq_domain); + irq_domain_remove(domain); } /** @@ -571,20 +563,20 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) return PTR_ERR(port->irq_domain); } - /* Setup MSI */ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - port->irq_domain = irq_domain_add_linear(node, - XILINX_NUM_MSI_IRQS, - &msi_domain_ops, - &xilinx_pcie_msi_chip); - if (!port->irq_domain) { - dev_err(dev, "Failed to get a MSI IRQ domain\n"); - return PTR_ERR(port->irq_domain); - } + if (!IS_ENABLED(CONFIG_PCI_MSI)) + return 0; - xilinx_pcie_enable_msi(port); + /* Setup MSI */ + port->msi_irq_domain = irq_domain_add_linear(node, + XILINX_NUM_MSI_IRQS, + &msi_domain_ops, + &xilinx_pcie_msi_chip); + if (!port->msi_irq_domain) { + dev_err(dev, "Failed to get a MSI IRQ domain\n"); + return PTR_ERR(port->msi_irq_domain); } + xilinx_pcie_enable_msi(port); return 0; } @@ -869,7 +861,13 @@ static int xilinx_pcie_remove(struct platform_device *pdev) { struct xilinx_pcie_port *port = platform_get_drvdata(pdev); - xilinx_pcie_free_irq_domain(port); + xilinx_pcie_free_irq_domain(port->irq_domain, 4); + + if (config_enabled(CONFIG_MSI)) { + free_pages(port->msi_pages, 0); + xilinx_pcie_free_irq_domain(port->msi_irq_domain, + XILINX_NUM_MSI_IRQS); + } return 0; }