From patchwork Wed Feb 3 11:30:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 8201341 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E831BBEEE5 for ; Wed, 3 Feb 2016 11:49:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BEF98201ED for ; Wed, 3 Feb 2016 11:49:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 211B020279 for ; Wed, 3 Feb 2016 11:49:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755396AbcBCLcy (ORCPT ); Wed, 3 Feb 2016 06:32:54 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:34970 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754892AbcBCLcv (ORCPT ); Wed, 3 Feb 2016 06:32:51 -0500 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Websense Email Security Gateway with ESMTPS id 3E880BFD97783; Wed, 3 Feb 2016 11:32:48 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 3 Feb 2016 11:32:49 +0000 Received: from localhost (10.100.200.105) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Wed, 3 Feb 2016 11:32:49 +0000 From: Paul Burton To: , Ralf Baechle CC: Paul Burton , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Michal Simek , "Jiang Liu" , Grygorii Strashko , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , , Russell Joyce , , Thomas Gleixner , "Jingoo Han" , Subject: [PATCH v2 07/15] PCI: xilinx: Clear interrupt FIFO during probe Date: Wed, 3 Feb 2016 11:30:37 +0000 Message-ID: <1454499045-5020-8-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> References: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.105] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP xilinx_pcie_init_port clears the pending interrupts in the interrupt decode register, but does not clear the interrupt FIFO. This would lead to spurious interrupts if any were present in the FIFO at probe time. Clear the interrupt FIFO prior to the interrupt decode register in order to start with a clean slate as expected. Signed-off-by: Paul Burton Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver") --- Changes in v2: - Add Fixes tag. drivers/pci/host/pcie-xilinx.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 1eb74a2..6c5a503 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -568,6 +568,8 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) */ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port) { + u32 val; + if (xilinx_pcie_link_is_up(port)) dev_info(port->dev, "PCIe Link is UP\n"); else @@ -577,6 +579,17 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port) pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK, XILINX_PCIE_REG_IMR); + /* Clear interrupt FIFO */ + while (1) { + val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); + + if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) + break; + + pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, + XILINX_PCIE_REG_RPIFR1); + } + /* Clear pending interrupts */ pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) & XILINX_PCIE_IMR_ALL_MASK,