From patchwork Mon Feb 8 12:41:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 8249281 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E194A9F3CD for ; Mon, 8 Feb 2016 12:42:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2957E203C2 for ; Mon, 8 Feb 2016 12:42:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1D7FC203A9 for ; Mon, 8 Feb 2016 12:42:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752779AbcBHMmk (ORCPT ); Mon, 8 Feb 2016 07:42:40 -0500 Received: from szxga02-in.huawei.com ([119.145.14.65]:63150 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752371AbcBHMmh (ORCPT ); Mon, 8 Feb 2016 07:42:37 -0500 Received: from 172.24.1.48 (EHLO szxeml431-hub.china.huawei.com) ([172.24.1.48]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DBB51337; Mon, 08 Feb 2016 20:42:08 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.156) by szxeml431-hub.china.huawei.com (10.82.67.208) with Microsoft SMTP Server id 14.3.235.1; Mon, 8 Feb 2016 20:41:58 +0800 From: Gabriele Paoloni To: , , , , , , , , CC: , , , , , , , , Subject: [RFC PATCH v2 2/3] PCI: hisi: Make the HiSilicon PCIe host controller ECAM compliant Date: Mon, 8 Feb 2016 12:41:03 +0000 Message-ID: <1454935264-6076-3-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1454935264-6076-1-git-send-email-gabriele.paoloni@huawei.com> References: <1454935264-6076-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.156] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.56B88D22.013F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 155f90b960db5ef4a50494f81a13e70e Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: gabriele paoloni This patch modifies the current Hip05/Hip06 PCIe host controller driver to make it ECAM compliant. This is needed in preparation for the ACPI based driver to allow both DT and ACPI drivers to use the same BIOS (that configure the Designware iATUs). Signed-off-by: Gabriele Paoloni Signed-off-by: Dongdong Liu --- drivers/pci/host/pcie-designware.c | 4 +--- drivers/pci/host/pcie-designware.h | 2 ++ drivers/pci/host/pcie-hisi.c | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 2171682..5f19ea4 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -69,8 +69,6 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C -static struct pci_ops dw_pcie_ops; - int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) { if ((uintptr_t)addr & (size - 1)) { @@ -690,7 +688,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); } -static struct pci_ops dw_pcie_ops = { +struct pci_ops dw_pcie_ops = { .read = dw_pcie_rd_conf, .write = dw_pcie_wr_conf, }; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 2356d29..3f42655 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -80,4 +80,6 @@ int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); +extern struct pci_ops dw_pcie_ops; + #endif /* _PCIE_DESIGNWARE_H */ diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c index 458d0f8..eb3201a 100644 --- a/drivers/pci/host/pcie-hisi.c +++ b/drivers/pci/host/pcie-hisi.c @@ -43,6 +43,18 @@ struct pcie_soc_ops { int (*hisi_pcie_link_up)(struct hisi_pcie *pcie); }; +static inline int hisi_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 *value) +{ + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static inline int hisi_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 value) +{ + return pci_generic_config_write(bus, devfn, where, size, value); +} + static inline int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size, u32 *val) { @@ -67,11 +79,24 @@ static int hisi_pcie_link_up(struct pcie_port *pp) } struct pcie_host_ops hisi_pcie_host_ops = { + .rd_other_conf = hisi_rd_other_conf, + .wr_other_conf = hisi_wr_other_conf, .rd_own_conf = hisi_pcie_cfg_read, .wr_own_conf = hisi_pcie_cfg_write, .link_up = hisi_pcie_link_up, }; +static void __iomem *hisi_pci_map_cfg_bus_cam(struct pci_bus *bus, + unsigned int devfn, + int where) +{ + void __iomem *addr; + struct pcie_port *pp = bus->sysdata; + + addr = pp->va_cfg1_base + where; + + return addr; +} static int hisi_add_pcie_port(struct pcie_port *pp, struct platform_device *pdev) @@ -92,6 +117,8 @@ static int hisi_add_pcie_port(struct pcie_port *pp, pp->ops = &hisi_pcie_host_ops; + dw_pcie_ops.map_bus = hisi_pci_map_cfg_bus_cam; + ret = dw_pcie_host_init(pp); if (ret) { dev_err(&pdev->dev, "failed to initialize host\n"); @@ -137,6 +164,14 @@ static int hisi_pcie_probe(struct platform_device *pdev) hisi_pcie->pp.dbi_base = hisi_pcie->reg_base; + reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam-cfg"); + hisi_pcie->pp.va_cfg0_base = devm_ioremap_resource(&pdev->dev, reg); + if (IS_ERR(hisi_pcie->pp.va_cfg0_base)) { + dev_err(pp->dev, "cannot get ecam-cfg\n"); + return PTR_ERR(hisi_pcie->pp.va_cfg0_base); + } + hisi_pcie->pp.va_cfg1_base = hisi_pcie->pp.va_cfg0_base; + ret = hisi_add_pcie_port(pp, pdev); if (ret) return ret;