From patchwork Thu Apr 28 21:27:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 8975061 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 58381BF440 for ; Thu, 28 Apr 2016 21:28:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8896520166 for ; Thu, 28 Apr 2016 21:28:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ABD1820212 for ; Thu, 28 Apr 2016 21:28:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753643AbcD1V2L (ORCPT ); Thu, 28 Apr 2016 17:28:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:44829 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753635AbcD1V2J (ORCPT ); Thu, 28 Apr 2016 17:28:09 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id ACAED6121C; Thu, 28 Apr 2016 21:28:07 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9F1BF61305; Thu, 28 Apr 2016 21:28:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from illium.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id ED29E612EF; Thu, 28 Apr 2016 21:28:04 +0000 (UTC) From: Christopher Covington To: Timur Tabi , Sinan Kaya , Mark Salter , Mark Langsdorf , Jon Masters Cc: linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Christopher Covington Subject: [PATCH] acpi: pci: QDF2432 32 bit config space accessors Date: Thu, 28 Apr 2016 17:27:38 -0400 Message-Id: <1461878858-23798-1-git-send-email-cov@codeaurora.org> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1460740008-19489-1-git-send-email-tn@semihalf.com> References: <1460740008-19489-1-git-send-email-tn@semihalf.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Qualcomm Technologies QDF2432 SoCs require 32 bit accessors to be used for the PCI configuration space. Register the appropriate quirk. Signed-off-by: Christopher Covington --- Depends on Tomasz Nowicki's latest series: [PATCH V6 00/13] Support for generic ACPI based PCI host controller --- drivers/acpi/pci_gen_host.c | 13 +++++++++++++ drivers/pci/ecam.c | 10 ++++++++++ drivers/pci/ecam.h | 3 +++ 3 files changed, 26 insertions(+) diff --git a/drivers/acpi/pci_gen_host.c b/drivers/acpi/pci_gen_host.c index e55dfca..daf8a86 100644 --- a/drivers/acpi/pci_gen_host.c +++ b/drivers/acpi/pci_gen_host.c @@ -257,3 +257,16 @@ int raw_pci_write(unsigned int domain, unsigned int busn, unsigned int devfn, return PCIBIOS_DEVICE_NOT_FOUND; return bus->ops->write(bus, devfn, reg, len, val); } + +static const struct dmi_system_id qcom_qdf2432[] = { + { + .ident = "Qualcomm Technologies QDF2432", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Qualcomm"), + DMI_MATCH(DMI_PRODUCT_NAME, "QDF2432"), + }, + }, + { } +}; + +DECLARE_ACPI_MCFG_FIXUP(qcom_qdf2432, NULL, &pci_generic_ecam_32b_ops, PCI_MCFG_DOMAIN_ANY, PCI_MCFG_BUS_ANY); diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c index ff04c01..720a038 100644 --- a/drivers/pci/ecam.c +++ b/drivers/pci/ecam.c @@ -135,3 +135,13 @@ struct pci_generic_ecam_ops pci_generic_ecam_default_ops = { .write = pci_generic_config_write, } }; + +/* ECAM ops with 32 bit config space access quirk */ +struct pci_generic_ecam_ops pci_generic_ecam_32b_ops = { + .bus_shift = 20, + .pci_ops = { + .map_bus = pci_generic_ecam_map_bus, + .read = pci_generic_config_read32, + .write = pci_generic_config_write32, + } +}; diff --git a/drivers/pci/ecam.h b/drivers/pci/ecam.h index 706621a..4af764f 100644 --- a/drivers/pci/ecam.h +++ b/drivers/pci/ecam.h @@ -58,6 +58,9 @@ void __iomem *pci_generic_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, /* default ECAM ops, bus shift 20, generic read and write */ extern struct pci_generic_ecam_ops pci_generic_ecam_default_ops; +/* ECAM ops with 32 bit config space access quirk */ +extern struct pci_generic_ecam_ops pci_generic_ecam_32b_ops; + #ifdef CONFIG_PCI_HOST_GENERIC /* for DT based pci controllers that support ECAM */ int pci_host_common_probe(struct platform_device *pdev,