From patchwork Fri May 20 10:29:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9129179 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7917E60762 for ; Fri, 20 May 2016 10:29:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 68AC127BF4 for ; Fri, 20 May 2016 10:29:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5AF59279C4; Fri, 20 May 2016 10:29:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E3629279C4 for ; Fri, 20 May 2016 10:29:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755887AbcETK33 (ORCPT ); Fri, 20 May 2016 06:29:29 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:34337 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755883AbcETK31 (ORCPT ); Fri, 20 May 2016 06:29:27 -0400 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.140]) by lucky1.263xmail.com (Postfix) with SMTP id CA2241EE973; Fri, 20 May 2016 18:29:19 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 19A294007; Fri, 20 May 2016 18:29:12 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: bhelgaas@google.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 20217BSCYKX; Fri, 20 May 2016 18:29:14 +0800 (CST) From: Shawn Lin To: Bjorn Helgaas Cc: Heiko Stuebner , Wenrui Li , Rob Herring , devicetree@vger.kernel.org, Doug Anderson , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Shawn Lin Subject: [PATCH 1/2] Documentation: add binding description of Rockchip PCIe controller Date: Fri, 20 May 2016 18:29:06 +0800 Message-Id: <1463740146-7106-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1463740105-7061-1-git-send-email-shawn.lin@rock-chips.com> References: <1463740105-7061-1-git-send-email-shawn.lin@rock-chips.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add some required and optional properties for Rockchip PCIe controller. Also we add a example for how to use it. Signed-off-by: Shawn Lin --- .../devicetree/bindings/pci/rockchip-pcie.txt | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rockchip-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt new file mode 100644 index 0000000..69a0804 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt @@ -0,0 +1,93 @@ +* Rockchip AXI PCIe Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to <3> +- #size-cells: Size representation for root ports, set to <2> +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain "rockchip,rk3399-pcie" +- reg: Two register ranges as listed in the reg-names property +- reg-names: The first entry must be "axi-base" for the core registers + The second entry must be "apb-base" for the client pcie registers +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - "aclk_pcie" + - "aclk_perf_pcie" + - "hclk_pcie" + - "clk_pciephy_ref" +- interrupts: Three interrupt entries must be specified. +- interrupt-names: Must include the following names + - "pcie-sys" + - "pcie-legacy" + - "pcie-client" +- resets: Must contain five entries for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following names + - "phy-rst" + - "core-rst" + - "mgmt-rst" + - "mgmt-sticky-rst" + - "pipe-rst" +- rockchip,grf: phandle to the syscon managing the "general register files" +- pcie-conf: offset of pcie client block for configuration +- pcie-status: offset of pcie client block for status +- pcie-laneoff: offset of pcie client block for lane +- msi-parent: Link to the hardware entity that serves as the Message +- pinctrl-names : The pin control state names +- pinctrl-0: The "default" pinctrl state +- interrupt-map-mask and interrupt-map: standard PCI properties +- interrupt-controller: identifies the node as an interrupt controller + +Optional Property: +- ep-gpios: contain the entry for pre-reset gpio +- num-lanes: number of lanes to use +- assigned-clocks, assigned-clock-parents and assigned-clock-rates: standard + clock bindings. See ../clock/clock-bindings.txt + +Example: + +pci_express: axi-pcie@f8000000 { + #address-cells = <3>; + #size-cells = <2>; + compatible = "rockchip,rk3399-pcie"; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>; + clock-names = "aclk_pcie", "aclk_perf_pcie", + "hclk_pcie", "clk_pciephy_ref"; + bus-range = <0x0 0x1>; + interrupts = , , + ; + interrupt-names: "pcie-sys", "pcie-legacy", "pcie-client"; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; + ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000 + 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >; + num-lanes = <4>; + reg = < 0x0 0xf8000000 0x0 0x2000000 >, < 0x0 0xfd000000 0x0 0x1000000 >; + reg-name = "axi-base", "apb-base"; + resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>; + reset-names = "phy-rst", "core-rst", "mgmt-rst", "mgmt-sticky-rst", "pipe-rst"; + rockchip,grf = <&grf>; + pcie-conf = <0xe220>; + pcie-status = <0xe2a4>; + pcie-laneoff = <0xe214>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq>; + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_0 1>, + <0 0 0 2 &pcie_0 2>, + <0 0 0 3 &pcie_0 3>, + <0 0 0 4 &pcie_0 4>; + pcie_0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + +};