From patchwork Wed Jun 1 12:31:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 9147301 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A460C60757 for ; Wed, 1 Jun 2016 12:33:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 96C6620093 for ; Wed, 1 Jun 2016 12:33:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8BB06269DE; Wed, 1 Jun 2016 12:33:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8338820093 for ; Wed, 1 Jun 2016 12:33:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758053AbcFAMdF (ORCPT ); Wed, 1 Jun 2016 08:33:05 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:64321 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757333AbcFAMdD (ORCPT ); Wed, 1 Jun 2016 08:33:03 -0400 Received: from wuerfel.lan. ([78.42.132.4]) by mrelayeu.kundenserver.de (mreue102) with ESMTPA (Nemesis) id 0M2MnE-1bONB51672-00s74U; Wed, 01 Jun 2016 14:32:02 +0200 From: Arnd Bergmann To: Bjorn Helgaas , Jingoo Han , Pratyush Anand Cc: Heiko Stuebner , Wenrui Li , Doug Anderson , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Shawn Lin , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Gabriele Paoloni , Zhou Wang , Lucas Stach , Jisheng Zhang , Lorenzo Pieralisi , Joao Pinto Subject: [PATCH 2/3] pci: dw: use new config space accessors Date: Wed, 1 Jun 2016 14:31:23 +0200 Message-Id: <1464784332-3775650-2-git-send-email-arnd@arndb.de> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1464784332-3775650-1-git-send-email-arnd@arndb.de> References: <1464784332-3775650-1-git-send-email-arnd@arndb.de> X-Provags-ID: V03:K0:89Phcbs/aUqx8tas5OStzRqGmPQ0Mv+Rs91Tq9NuCTYPwG6HKNN aZCXOrNB68CJDQegcJiZ6ENmAkHZnC5h94x3Fs2UbwbXWuREiblkwdRcARex5hBaKokWby9 WgJq0vDoWJ+Krmik9jUkmXhmVz3wMzqPM/M48AlOpItxk8jfm+J8fTo7VxQvPpuInhbZkOE LCEtaiOZ9XMQveAgAxlng== X-UI-Out-Filterresults: notjunk:1; V01:K0:mbfFkjdDVjU=:PkGBBUKbJDOnZrbKr9eG10 CjsX6QjaJIeqcryRsX/SDIIQfPmUi3s6Ki+3XkKSraPeT4dCk60L93zEjOpZHn+l1GAZf2XHD tGjNGATLpaV+vGLV6YgbnSh6e9FtdTPgu0SvpFWp4Bo45Fl4bjBMKUEfJsgRSeYAbbeplXeoY RK5hU9Wd0vJMFJW032tLG1nM3rsgPaUfKGV/t0kXK88VBmN43Wx0Kt6fMwCZWgi6N9/d2fuch w+sN8USTZ2m8R8qZUGSplIE6msD9PVTIeqt+Fq3AsGeDAXW4nKsHdjL43sU5rxywDNmUVuv3C 9C24rOwHqnIHyC35puRsuPebKUpadRvBp5Mf+yQstn1uFd3zWMe9dwotvl9zjrxDJbqoWfXtA wzVgtv/ntLQC2LFkLnJZDlmOVHKP/r8p+jPio2cH2mmLy1l1lM/3ha7mtlDbBne4m24P6Qahe ZUz46/YTPudBK6gxOp0d5lYzKOIY6N8Cfzifb+Gskqm1YV7yYtWeapPoLloedMbbKhbm+/vCX gSoJa/dnL1XL9JwerUKyOa5SHkQjMYh1ZW3bTLpEctukyf8EPZLlNZCbzpLJCnwIatDlfnGEK NX11JD+rYsBnRK7dTsu37boI98DhpLN5egBCkEZpA0WqjlUrDsAtuRtnMoYaSqTrQqtKPhyAO z4BSorbt9zDyc7WJhZnSUyYQFzORQHdcRvlGNCDhkDFDh5tlj38vwAARcrqIQ264wrnU= Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PCI core can now use separate callbacks for type 1 config space accesses, so we can simplify the dw_pcie_wr_conf/dw_pcie_rd_conf logic that multiplexes between the two kinds. Signed-off-by: Arnd Bergmann --- drivers/pci/host/pcie-designware.c | 73 +++++++++++++++----------------------- 1 file changed, 28 insertions(+), 45 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index aafd766546f3..37e16c159719 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -573,13 +573,24 @@ int dw_pcie_host_init(struct pcie_port *pp) return 0; } -static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, +static int dw_pcie_rd_other_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { int ret, type; u32 busdev, cfg_size; u64 cpu_addr; void __iomem *va_cfg_base; + struct pcie_port *pp = bus->sysdata; + + /* + * If there is no link, then there is no device. + * + * do not read more than one device on the bus directly attached + * to RC's (Virtual Bridge's) DS side. + */ + if (!dw_pcie_link_up(pp) || + (bus->primary == pp->root_bus_nr && PCI_SLOT(devfn) > 0)) + return PCIBIOS_DEVICE_NOT_FOUND; if (pp->ops->rd_other_conf) return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); @@ -610,13 +621,18 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, return ret; } -static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, +static int dw_pcie_wr_other_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { int ret, type; u32 busdev, cfg_size; u64 cpu_addr; void __iomem *va_cfg_base; + struct pcie_port *pp = bus->sysdata; + + if (!dw_pcie_link_up(pp) || + (bus->primary == pp->root_bus_nr && PCI_SLOT(devfn) > 0)) + return PCIBIOS_DEVICE_NOT_FOUND; if (pp->ops->wr_other_conf) return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); @@ -647,62 +663,29 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, return ret; } -static int dw_pcie_valid_config(struct pcie_port *pp, - struct pci_bus *bus, int dev) -{ - /* If there is no link, then there is no device */ - if (bus->number != pp->root_bus_nr) { - if (!dw_pcie_link_up(pp)) - return 0; - } - - /* access only one slot on each root port */ - if (bus->number == pp->root_bus_nr && dev > 0) - return 0; - - /* - * do not read more than one device on the bus directly attached - * to RC's (Virtual Bridge's) DS side. - */ - if (bus->primary == pp->root_bus_nr && dev > 0) - return 0; - - return 1; -} - -static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, +static int dw_pcie_rd_bridge_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus->sysdata; - - if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { - *val = 0xffffffff; + if (PCI_SLOT(devfn) > 0) return PCIBIOS_DEVICE_NOT_FOUND; - } - - if (bus->number == pp->root_bus_nr) - return dw_pcie_rd_own_conf(pp, where, size, val); - return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); + return dw_pcie_rd_own_conf(bus->sysdata, where, size, val); } -static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, +static int dw_pcie_wr_bridge_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus->sysdata; - - if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) + if (PCI_SLOT(devfn) > 0) return PCIBIOS_DEVICE_NOT_FOUND; - if (bus->number == pp->root_bus_nr) - return dw_pcie_wr_own_conf(pp, where, size, val); - - return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); + return dw_pcie_wr_own_conf(bus->sysdata, where, size, val); } static struct pci_ops dw_pcie_ops = { - .read = dw_pcie_rd_conf, - .write = dw_pcie_wr_conf, + .read_bridge = dw_pcie_rd_bridge_conf, + .write_bridge = dw_pcie_wr_bridge_conf, + .read = dw_pcie_rd_other_conf, + .write = dw_pcie_wr_other_conf, }; void dw_pcie_setup_rc(struct pcie_port *pp)