From patchwork Thu Jul 14 10:10:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christophe JAILLET X-Patchwork-Id: 9229505 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 20AEA607D0 for ; Thu, 14 Jul 2016 10:12:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 110D127D5D for ; Thu, 14 Jul 2016 10:12:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0575328066; Thu, 14 Jul 2016 10:12:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 150EF27D5D for ; Thu, 14 Jul 2016 10:12:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751093AbcGNKMX (ORCPT ); Thu, 14 Jul 2016 06:12:23 -0400 Received: from smtp04.smtpout.orange.fr ([80.12.242.126]:22846 "EHLO smtp.smtpout.orange.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751025AbcGNKMV convert rfc822-to-8bit (ORCPT ); Thu, 14 Jul 2016 06:12:21 -0400 Received: from localhost.localdomain ([92.140.225.101]) by mwinf5d39 with ME id JaCG1t00C2BtL5o03aCGgc; Thu, 14 Jul 2016 12:12:19 +0200 X-ME-Helo: localhost.localdomain X-ME-Auth: Y2hyaXN0b3BoZS5qYWlsbGV0QHdhbmFkb28uZnI= X-ME-Date: Thu, 14 Jul 2016 12:12:19 +0200 X-ME-IP: 92.140.225.101 From: Christophe JAILLET To: bhelgaas@google.com, michal.simek@xilinx.com, soren.brinkmann@xilinx.com, bharat.kumar.gogada@xilinx.com, rgummal@xilinx.com, arnd@arndb.de, jiang.liu@linux.intel.com, grygorii.strashko@ti.com, russell.joyce@york.ac.uk, lorenzo.pieralisi@arm.com Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org, Christophe JAILLET Subject: [PATCH] PCI: xilinx: Fix return value in case of error Date: Thu, 14 Jul 2016 12:10:46 +0200 Message-Id: <1468491046-1427-1-git-send-email-christophe.jaillet@wanadoo.fr> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Antivirus: avast! (VPS 160714-0, 14/07/2016), Outbound message X-Antivirus-Status: Clean Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In function 'xilinx_pcie_init_irq_domain', the pattern used to check and return error is: if (!var) { dev_err(...); return PTR_ERR(var); } So the returned value in case of error is always 0, which means 'success'. Change it to return -ENODEV instead. Signed-off-by: Christophe JAILLET Acked-by: Sören Brinkmann --- drivers/pci/host/pcie-xilinx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 4703aa3..a30e016 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -550,7 +550,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) pcie_intc_node = of_get_next_child(node, NULL); if (!pcie_intc_node) { dev_err(dev, "No PCIe Intc node found\n"); - return PTR_ERR(pcie_intc_node); + return -ENODEV; } port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4, @@ -558,7 +558,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) port); if (!port->irq_domain) { dev_err(dev, "Failed to get a INTx IRQ domain\n"); - return PTR_ERR(port->irq_domain); + return -ENODEV; } /* Setup MSI */ @@ -569,7 +569,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) &xilinx_pcie_msi_chip); if (!port->irq_domain) { dev_err(dev, "Failed to get a MSI IRQ domain\n"); - return PTR_ERR(port->irq_domain); + return -ENODEV; } xilinx_pcie_enable_msi(port);