From patchwork Tue Aug 30 12:57:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 9305381 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BDD25607F0 for ; Tue, 30 Aug 2016 12:57:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE37328BB6 for ; Tue, 30 Aug 2016 12:57:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A2E0E28BCB; Tue, 30 Aug 2016 12:57:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0754028BC3 for ; Tue, 30 Aug 2016 12:57:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758411AbcH3M50 (ORCPT ); Tue, 30 Aug 2016 08:57:26 -0400 Received: from down.free-electrons.com ([37.187.137.238]:55600 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1758437AbcH3M5W (ORCPT ); Tue, 30 Aug 2016 08:57:22 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 3EBDA303; Tue, 30 Aug 2016 14:57:20 +0200 (CEST) Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id EEFA62DE; Tue, 30 Aug 2016 14:57:19 +0200 (CEST) From: Thomas Petazzoni To: Joao Pinto , Bjorn Helgaas , Jingoo Han , Pratyush Anand , linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , linux-arm-kernel@lists.infradead.org, Yehuda Yitschak , Shadi Ammouri , Nadav Haklai , Thomas Petazzoni Subject: [PATCH 2/3] pci: pcie-designware: add support for external MSI controller Date: Tue, 30 Aug 2016 14:57:09 +0200 Message-Id: <1472561830-20932-3-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472561830-20932-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1472561830-20932-1-git-send-email-thomas.petazzoni@free-electrons.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Designware PCIe controllers have a built-in MSI controller, which is already supported by the existing. However, in some situations, it might be a better choice to use an external MSI controller, especially when it provides a higher number of MSI interrupts than the built-in one. Therefore, this commit extends the pcie-designware driver to support the "msi-parent" DT property, already used by other drivers. It contains a phandle pointing to the external MSI controller to be used. Following this commit, the pcie-designware code supports three possibilities, in this order: 1. If msi-parent is provided, then the MSI controller pointed by this property is used. 2. Otherwise, and if no ->msi_host_init() function is provided by the platform-specific "glue", then the built-in MSI controller of the Designware controller is used. 3. Otherwise, the ->msi_host_init() function of the platform-specific "glue" is used to do some additional initialization, but it's still the built-in MSI controller that is used. Signed-off-by: Thomas Petazzoni --- drivers/pci/host/pcie-designware.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 12afce1..1e18a85 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -437,6 +437,7 @@ int dw_pcie_host_init(struct pcie_port *pp) int i, ret; LIST_HEAD(res); struct resource_entry *win; + struct msi_controller *msi = NULL; cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (cfg_res) { @@ -525,10 +526,21 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->lanes = 0; if (IS_ENABLED(CONFIG_PCI_MSI)) { - if (!pp->ops->msi_host_init) { + if (of_find_property(pp->dev->of_node, "msi-parent", NULL)) { + struct device_node *msi_node; + + msi_node = of_parse_phandle(pp->dev->of_node, + "msi-parent", 0); + if (!msi_node) + return -ENODEV; + + msi = of_pci_find_msi_chip_by_node(msi_node); + } else if (!pp->ops->msi_host_init) { + msi = &dw_pcie_msi_chip; + msi->dev = pp->dev; pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, MAX_MSI_IRQS, &msi_domain_ops, - &dw_pcie_msi_chip); + msi); if (!pp->irq_domain) { dev_err(pp->dev, "irq domain init failed\n"); ret = -ENXIO; @@ -538,7 +550,9 @@ int dw_pcie_host_init(struct pcie_port *pp) for (i = 0; i < MAX_MSI_IRQS; i++) irq_create_mapping(pp->irq_domain, i); } else { - ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); + msi = &dw_pcie_msi_chip; + msi->dev = pp->dev; + ret = pp->ops->msi_host_init(pp, msi); if (ret < 0) goto error; } @@ -550,9 +564,7 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->root_bus_nr = pp->busn->start; if (IS_ENABLED(CONFIG_PCI_MSI)) { bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr, - &dw_pcie_ops, pp, &res, - &dw_pcie_msi_chip); - dw_pcie_msi_chip.dev = pp->dev; + &dw_pcie_ops, pp, &res, msi); } else bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, pp, &res);