From patchwork Thu Sep 1 23:00:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Kaya X-Patchwork-Id: 9310131 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CBADF60760 for ; Thu, 1 Sep 2016 23:00:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CC43F29559 for ; Thu, 1 Sep 2016 23:00:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C10242956D; Thu, 1 Sep 2016 23:00:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BE3C42956C for ; Thu, 1 Sep 2016 23:00:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754506AbcIAXAP (ORCPT ); Thu, 1 Sep 2016 19:00:15 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60632 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754504AbcIAXAN (ORCPT ); Thu, 1 Sep 2016 19:00:13 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 20ED361F36; Thu, 1 Sep 2016 23:00:12 +0000 (UTC) Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 812FE61F0F; Thu, 1 Sep 2016 23:00:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 812FE61F0F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: linux-pci@vger.kernel.org, timur@codeaurora.org, cov@codeaurora.org, alex.williamson@redhat.com, vikrams@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , linux-kernel@vger.kernel.org Subject: [PATCH 1/2] PCI: save and restore device state during bus reset Date: Thu, 1 Sep 2016 19:00:00 -0400 Message-Id: <1472770801-30671-1-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 1.9.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A secondary bus reset causes settings to be lost by all downstream devices on the tree. The code is currently saving and restoring device states only when called from the VFIO path via pci_probe_reset_bus and pci_reset_bus functions. Moving the save and restore into pci_reset_bridge_secondary_bus so that all users of the API have the same behavior. Signed-off-by: Sinan Kaya --- drivers/pci/pci.c | 36 +++++++++++++++--------------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index aab9d51..b209378 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3860,19 +3860,6 @@ void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) pci_reset_secondary_bus(dev); } -/** - * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. - * @dev: Bridge device - * - * Use the bridge control register to assert reset on the secondary bus. - * Devices on the secondary bus are left in power-on state. - */ -void pci_reset_bridge_secondary_bus(struct pci_dev *dev) -{ - pcibios_reset_secondary_bus(dev); -} -EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); - static int pci_parent_bus_reset(struct pci_dev *dev, int probe) { struct pci_dev *pdev; @@ -4362,6 +4349,21 @@ static void pci_slot_restore(struct pci_slot *slot) } } +/** + * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. + * @dev: Bridge device + * + * Use the bridge control register to assert reset on the secondary bus. + * Devices on the secondary bus are left in power-on state. + */ +void pci_reset_bridge_secondary_bus(struct pci_dev *dev) +{ + pci_bus_save_and_disable(dev->bus); + pcibios_reset_secondary_bus(dev); + pci_bus_restore(dev->bus); +} +EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); + static int pci_slot_reset(struct pci_slot *slot, int probe) { int rc; @@ -4504,12 +4506,8 @@ int pci_reset_bus(struct pci_bus *bus) if (rc) return rc; - pci_bus_save_and_disable(bus); - rc = pci_bus_reset(bus, 0); - pci_bus_restore(bus); - return rc; } EXPORT_SYMBOL_GPL(pci_reset_bus); @@ -4528,8 +4526,6 @@ int pci_try_reset_bus(struct pci_bus *bus) if (rc) return rc; - pci_bus_save_and_disable(bus); - if (pci_bus_trylock(bus)) { might_sleep(); pci_reset_bridge_secondary_bus(bus->self); @@ -4537,8 +4533,6 @@ int pci_try_reset_bus(struct pci_bus *bus) } else rc = -EAGAIN; - pci_bus_restore(bus); - return rc; } EXPORT_SYMBOL_GPL(pci_try_reset_bus);