From patchwork Wed Oct 12 02:01:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9371931 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 226BC60487 for ; Wed, 12 Oct 2016 01:55:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 10FF828E63 for ; Wed, 12 Oct 2016 01:55:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 041AC28F5B; Wed, 12 Oct 2016 01:55:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 98E8228E63 for ; Wed, 12 Oct 2016 01:55:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932994AbcJLBzd (ORCPT ); Tue, 11 Oct 2016 21:55:33 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:39628 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754786AbcJLBzZ (ORCPT ); Tue, 11 Oct 2016 21:55:25 -0400 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.154]) by lucky1.263xmail.com (Postfix) with ESMTP id DC9D61EEA8B; Wed, 12 Oct 2016 09:55:13 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED4: 1 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 290473C2; Wed, 12 Oct 2016 09:55:07 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: bhelgaas@google.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <72d43d7f54baf57738f94f0a2a8f087a> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 30440T1H05H; Wed, 12 Oct 2016 09:55:11 +0800 (CST) From: Shawn Lin To: Bjorn Helgaas , Rob Herring Cc: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Rajat Jain , Wenrui Li , Brian Norris , devicetree@vger.kernel.org, Shawn Lin Subject: [PATCH v7 1/3] Documentation/devicetree: Add new property to specify the max link speed Date: Wed, 12 Oct 2016 10:01:23 +0800 Message-Id: <1476237685-14539-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.8.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of the host drivers have the requirement of knowing whether the EP would never train at some link speed at all. For instance, on some boards, the link won't train at 5 GT/s but the host driver still sacrifice some cycle to wait for the resule of training at 5 GT/s as the host could actually support 5 GT/s. So we could parse this new property and make the host drivers be aware of these cases. Signed-off-by: Shawn Lin --- Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 08dcfad..e7d97a3 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -18,3 +18,9 @@ driver implementation may support the following properties: host bridges in the system, otherwise potentially conflicting domain numbers may be assigned to root buses behind different host bridges. The domain number for each host bridge in the system must be unique. +- max-link-speed: + If present this property specifies PCI gen for link capability. The host drivers + could add this as a strategy to avoid unnecessary operation for unsupported + link speed, for instance, trying to do training for unsupported link speed, etc. + Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other + values are invalid.