From patchwork Mon Oct 24 22:17:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 9393363 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A3052607F0 for ; Mon, 24 Oct 2016 22:18:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 944A029183 for ; Mon, 24 Oct 2016 22:18:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 87CB32917D; Mon, 24 Oct 2016 22:18:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0086629183 for ; Mon, 24 Oct 2016 22:18:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965478AbcJXWR6 (ORCPT ); Mon, 24 Oct 2016 18:17:58 -0400 Received: from mail-pf0-f170.google.com ([209.85.192.170]:36183 "EHLO mail-pf0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965477AbcJXWRx (ORCPT ); Mon, 24 Oct 2016 18:17:53 -0400 Received: by mail-pf0-f170.google.com with SMTP id e6so105849533pfk.3 for ; Mon, 24 Oct 2016 15:17:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9APrDW3yp3iYDRH0T+tFV9QOamGPzB3ITN1R3TPaUgY=; b=fvvrqwo2Y9LAhelCsliLqnYJerQOE+xtD4c9GxPasZFUNj/R9aPraZqrVkrqVYm1jB RshOS0Epm/0PxZvbPU0ZvMkYa+/qJexGFmxai3Z8OfiCOxu5NFBu/6J8LQE/FNUicljK vojPUL7L/T/uqCgkAaj4QjDhEOe3uv2bvvpd0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9APrDW3yp3iYDRH0T+tFV9QOamGPzB3ITN1R3TPaUgY=; b=kEfYU9ODxY7ezXJ0uWPFzMqtQ8+UTZNI7M0e3Z3Mypoa6KDsV42U3GgybasnMbA2E3 i2TJEHYffil+Gio21qjaQZxfbWIIlIyBnN3Ei9H/ifUfmgyeNVE+95KboZWfhT5dPfvn hL8WtcKA0DCeDYtSmmS+Winvf4tTKp9R+c/DXtvnfn5aQykMw6suMiTn+81eyV91SGeV U1ICj6KJ1Rwhsh02+PhItqqpzVHpyHFwFIhDYliB0q5ZOA/jINPr2mM+hy3Md1X3eYfq pkmCeZBRXom0G/qur6x2me6oYb1YInbqCLme2vYdSUbqAjd4SCBGrw8j1owk0ZRxl5cj DSFA== X-Gm-Message-State: ABUngvfcGBent38VhmsU5/8j0yF1iQJwlQWnNT0zoihSmY/2H1iBY92+wa31f+m56yRV77fu X-Received: by 10.99.251.69 with SMTP id w5mr27309146pgj.108.1477347472727; Mon, 24 Oct 2016 15:17:52 -0700 (PDT) Received: from lbrmn-lnxub44-1.ric.broadcom.com ([216.31.219.19]) by smtp.gmail.com with ESMTPSA id x1sm27745131pax.7.2016.10.24.15.17.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 24 Oct 2016 15:17:52 -0700 (PDT) From: Ray Jui To: Bjorn Helgaas , Bjorn Helgaas Cc: linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, Alex Barba , Oza Oza , Ray Jui , Ray Jui Subject: [PATCH 05/12] PCI: iproc: Update iProc PCIe DT binding Date: Mon, 24 Oct 2016 15:17:05 -0700 Message-Id: <1477347432-17656-6-git-send-email-ray.jui@broadcom.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1477347432-17656-1-git-send-email-ray.jui@broadcom.com> References: <1477347432-17656-1-git-send-email-ray.jui@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add new compatible string "brcm,iproc-pcie-paxc-v2" to the iProc PCIe device tree binding document. "brcm,iproc-pcie-paxc-v2" is for the second generation of the Broadcom iProc PCIe PAXC host controller Also updated the binding document with more detailed description of each compatible string and compatible SoCs Finally, added description of optional property "msi-map", for use with MSI controllers with sideband data Signed-off-by: Ray Jui Reviewed-by: Scott Branden --- .../devicetree/bindings/pci/brcm,iproc-pcie.txt | 31 ++++++++++++++++------ 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt index 01b88f4..071bbc2 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt @@ -1,10 +1,15 @@ * Broadcom iProc PCIe controller with the platform bus interface Required properties: -- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc" - for PAXC. PAXB-based root complex is used for external endpoint devices. - PAXC-based root complex is connected to emulated endpoint devices - internal to the ASIC +- compatible: + "brcm,iproc-pcie" for the first generation of PAXB based controller, +used in SoCs including NSP, Cygnus, NS2, and Pegasus + "brcm,iproc-pcie-paxc" for the first generation of PAXC based +controller, used in NS2 + "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based +controller, used in Stingray + PAXB-based root complex is used for external endpoint devices. PAXC-based +root complex is connected to emulated endpoint devices internal to the ASIC - reg: base address and length of the PCIe controller I/O register space - #interrupt-cells: set to <1> - interrupt-map-mask and interrupt-map, standard PCI properties to define the @@ -19,6 +24,7 @@ Required properties: Optional properties: - phys: phandle of the PCIe PHY device - phy-names: must be "pcie-phy" +- dma-coherent: present if DMA operations are coherent - brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done by the ASIC after power on reset. In this case, SW needs to configure it @@ -41,10 +47,19 @@ For older platforms without MSI integrated in the GIC, iProc PCIe core provides an event queue based MSI support. The iProc MSI uses host memories to store MSI posted writes in the event queues -- msi-parent: Link to the device node of the MSI controller. On newer iProc -platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc -platforms without MSI support in its interrupt controller, one may use the -event queue based MSI support integrated within the iProc PCIe core. +On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used + +- msi-map: Maps a Requester ID to an MSI controller and associated MSI +sideband data + +- msi-parent: Link to the device node of the MSI controller, used when no MSI +sideband data is passed between the iProc PCIe controller and the MSI +controller + +Refer to the following binding documents for more detailed description on +the use of 'msi-map' and 'msi-parent': + Documentation/devicetree/bindings/pci/pci-msi.txt + Documentation/devicetree/bindings/interrupt-controller/msi.txt When the iProc event queue based MSI is used, one needs to define the following properties in the MSI device node: