From patchwork Mon Apr 10 11:58:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongji Xie X-Patchwork-Id: 9672481 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DFB1A60244 for ; Mon, 10 Apr 2017 12:02:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D5CDD27CAF for ; Mon, 10 Apr 2017 12:02:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C82B728449; Mon, 10 Apr 2017 12:02:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66CE127CAF for ; Mon, 10 Apr 2017 12:02:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753229AbdDJMCn (ORCPT ); Mon, 10 Apr 2017 08:02:43 -0400 Received: from mail-pg0-f67.google.com ([74.125.83.67]:36544 "EHLO mail-pg0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753165AbdDJMCm (ORCPT ); Mon, 10 Apr 2017 08:02:42 -0400 Received: by mail-pg0-f67.google.com with SMTP id 81so25493353pgh.3 for ; Mon, 10 Apr 2017 05:02:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q4spo6iE8HRa94wJelzJsi52is9djViIUIbZ6gYX4zg=; b=X/3Z+sDJI77ljpUh4weHscK02VQwJPEjscZZaRFM4l5RQFtKiBTskYEeL2XdZo1xQK kq0UoaZ34V9PC9RgU3HE4wpqE7uFdbtIRH9Bnent0x49TOKGl6md7I9NIYWnOhuVK6wk b2/75UrkW2yujmyO/pYpzqgcPo0FaOoLAVvqRZt3/byoKQC4CCX4XEsRxTHN3ODgC47o 4BIobv21o5kv4NYOv2ep3BALH6CSiEktYco9kRj5RjXMyaau/MQwupnF5hC9kK+jrlW2 +FTJQRaLYupkZUuknUzCJl9wbI+xXrgmI4wjri4prfEFBz+n7jcE/dfKZ8DPzEnzw3eZ PesQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q4spo6iE8HRa94wJelzJsi52is9djViIUIbZ6gYX4zg=; b=AYOYBdRPYL6Vii2GEJ94f7pJI4HeoY7RJWyik99tx5xl8xDPQBKaQUw2gK0dGZfLtT hlFUXHKdjailXD0WbcIYFARp4Jz34YtbCL/cldZlR7ftrZq/2CNzGIWKAwOnvKBOcdjA y8xKoZkXb2+wEcD7brRDsDjaj6oQ8574EEXCSWIC6S4HbIjBGT9QdvEPuL0fLWrj4BEG 6XTzCHNK0w8k5XnZLFt/pBx1pFj/Za0uMGXwQjltZyTghJQoRmQsAQ8kgZxURbGdtJgy ex8ZTYPbbCmX7FulenF+ML5xE/OfpE/5tDE1J5nIDTLP7d3dFRBTm2M6A+Cv3L+5BZRB GUHg== X-Gm-Message-State: AFeK/H0dY47Mg3odOVpUlHt80olS6pM1MVGWf6gKqt8RpbuetiCHWwHqVc5hclQjpf5b9w== X-Received: by 10.99.149.65 with SMTP id t1mr37865267pgn.152.1491825757240; Mon, 10 Apr 2017 05:02:37 -0700 (PDT) Received: from localhost ([116.247.112.152]) by smtp.gmail.com with ESMTPSA id q136sm18333789pfq.80.2017.04.10.05.02.36 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Mon, 10 Apr 2017 05:02:36 -0700 (PDT) From: Yongji Xie To: bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, alex.williamson@redhat.com, gwshan@linux.vnet.ibm.com, aik@ozlabs.ru, benh@kernel.crashing.org, mpe@ellerman.id.au, paulus@samba.org, zhong@linux.vnet.ibm.com Subject: [PATCH v10 3/4] powerpc/powernv: Override pcibios_default_alignment() to force PCI devices to be page aligned Date: Mon, 10 Apr 2017 19:58:13 +0800 Message-Id: <1491825494-19331-4-git-send-email-elohimes@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1491825494-19331-1-git-send-email-elohimes@gmail.com> References: <1491825494-19331-1-git-send-email-elohimes@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This overrides pcibios_default_alignment() to set default alignment to PAGE_SIZE for all PCI devices on PowerNV platform. Thus sub-page BARs would not share a page and could be mapped into guest when VFIO passthrough them. Signed-off-by: Yongji Xie --- arch/powerpc/include/asm/machdep.h | 2 ++ arch/powerpc/kernel/pci-common.c | 8 ++++++++ arch/powerpc/platforms/powernv/pci-ioda.c | 7 +++++++ 3 files changed, 17 insertions(+) diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h index 5011b69..a82c192 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h @@ -173,6 +173,8 @@ struct machdep_calls { /* Called after scan and before resource survey */ void (*pcibios_fixup_phb)(struct pci_controller *hose); + resource_size_t (*pcibios_default_alignment)(struct pci_dev *); + #ifdef CONFIG_PCI_IOV void (*pcibios_fixup_sriov)(struct pci_dev *pdev); resource_size_t (*pcibios_iov_resource_alignment)(struct pci_dev *, int resno); diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index ffda24a..ceda574 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -233,6 +233,14 @@ void pcibios_reset_secondary_bus(struct pci_dev *dev) pci_reset_secondary_bus(dev); } +resource_size_t pcibios_default_alignment(struct pci_dev *pdev) +{ + if (ppc_md.pcibios_default_alignment) + return ppc_md.pcibios_default_alignment(pdev); + + return 0; +} + #ifdef CONFIG_PCI_IOV resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) { diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index e367382..354c852 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -3297,6 +3297,11 @@ static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) } } +static resource_size_t pnv_pci_default_alignment(struct pci_dev *pdev) +{ + return PAGE_SIZE; +} + #ifdef CONFIG_PCI_IOV static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno) @@ -3830,6 +3835,8 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np, hose->controller_ops = pnv_pci_ioda_controller_ops; } + ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; + #ifdef CONFIG_PCI_IOV ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;