From patchwork Fri Jun 16 08:17:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9790825 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 18B9860326 for ; Fri, 16 Jun 2017 08:20:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A463285DC for ; Fri, 16 Jun 2017 08:20:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F38CA2860C; Fri, 16 Jun 2017 08:20:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA13C2860F for ; Fri, 16 Jun 2017 08:20:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752899AbdFPIU1 (ORCPT ); Fri, 16 Jun 2017 04:20:27 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:59933 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752900AbdFPIU0 (ORCPT ); Fri, 16 Jun 2017 04:20:26 -0400 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.230]) by lucky1.263xmail.com (Postfix) with ESMTP id 2D2F41EEFC5; Fri, 16 Jun 2017 16:20:16 +0800 (CST) X-263anti-spam: X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id DF11F393; Fri, 16 Jun 2017 16:20:15 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: kishon@ti.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 21936NXT6U5; Fri, 16 Jun 2017 16:20:16 +0800 (CST) From: Shawn Lin To: Kishon Vijay Abraham I , Bjorn Helgaas Cc: Heiko Stuebner , linux-rockchip@lists.infradead.org, Brian Norris , linux-pci@vger.kernel.org, Shawn Lin Subject: [PATCH 1/2] phy-rockchip-pcie: add set_mode callback Date: Fri, 16 Jun 2017 16:17:47 +0800 Message-Id: <1497601068-181656-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.9.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP phy_mode was added for switching USB mode purposely as well as phy_set_mode API. However other types of PHY could also have some miscellaneous setting/modes need to be handled. This patch is gonna support this callback for phy-rockchip-pcie and do some power-saving work there. Note that we just stuff in some other values other that the existing phy_mode and convert it in the coressponding driver instead, otherwise we should extend the phy_mode again which it doesn't make sense to add in new driver's specificed value. Overall it looks fine to me as the controller's driver and the phy's driver are paired so that the caller and the consumer should be able to keep the value(mode) in consistent. Signed-off-by: Shawn Lin --- drivers/phy/rockchip/phy-rockchip-pcie.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c index 6904633..9ffad15 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -255,11 +255,33 @@ static int rockchip_pcie_phy_exit(struct phy *phy) return 0; } +static int rockchip_pcie_phy_set_mode(struct phy *phy, enum phy_mode mode) +{ + struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy); + u8 map = (u8)mode; + int i; + + for (i = 0; i < PHY_MAX_LANE_NUM; i++) { + if (map & BIT(i)) + continue; + + dev_dbg(&phy->dev, "idling lane %d\n", i); + regmap_write(rk_phy->reg_base, + rk_phy->phy_data->pcie_laneoff, + HIWORD_UPDATE(PHY_LANE_IDLE_OFF, + PHY_LANE_IDLE_MASK, + PHY_LANE_IDLE_A_SHIFT + i)); + } + + return 0; +} + static const struct phy_ops ops = { .init = rockchip_pcie_phy_init, .exit = rockchip_pcie_phy_exit, .power_on = rockchip_pcie_phy_power_on, .power_off = rockchip_pcie_phy_power_off, + .set_mode = rockchip_pcie_phy_set_mode, .owner = THIS_MODULE, };