From patchwork Wed Jul 19 07:27:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9850619 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1A513602C8 for ; Wed, 19 Jul 2017 07:28:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 08F8D285E3 for ; Wed, 19 Jul 2017 07:28:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F1CE928616; Wed, 19 Jul 2017 07:28:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 49E74285E3 for ; Wed, 19 Jul 2017 07:28:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752109AbdGSH2F (ORCPT ); Wed, 19 Jul 2017 03:28:05 -0400 Received: from lucky1.263xmail.com ([211.157.147.133]:37380 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751754AbdGSH2F (ORCPT ); Wed, 19 Jul 2017 03:28:05 -0400 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.228]) by lucky1.263xmail.com (Postfix) with ESMTP id 2ADA28F319; Wed, 19 Jul 2017 15:28:02 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 3F4003C1; Wed, 19 Jul 2017 15:28:01 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: kishon@ti.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 131054PURDV; Wed, 19 Jul 2017 15:28:03 +0800 (CST) From: Shawn Lin To: Kishon Vijay Abraham I , Bjorn Helgaas Cc: Rob Herring , Heiko Stuebner , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Norris , Jeffy Chen , Shawn Lin Subject: [RFC PATCH v4 7/7] dt-bindings: phy: convert to use per-lane Rockchip PCIe PHY Date: Wed, 19 Jul 2017 15:27:38 +0800 Message-Id: <1500449258-101663-3-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500449258-101663-1-git-send-email-shawn.lin@rock-chips.com> References: <1500448979-93067-1-git-send-email-shawn.lin@rock-chips.com> <1500449258-101663-1-git-send-email-shawn.lin@rock-chips.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch deprecate the legacy PCIe PHY and encourage user to use per-lane PHY mode by setting #phy-cells to 1. Signed-off-by: Shawn Lin Acked-by: Rob Herring Reviewed-by: Brian Norris --- Changes in v4: None Changes in v3: - rename the commit tile Changes in v2: None Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt index 0f6222a..b496042 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt @@ -3,7 +3,6 @@ Rockchip PCIE PHY Required properties: - compatible: rockchip,rk3399-pcie-phy - - #phy-cells: must be 0 - clocks: Must contain an entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must be "refclk" @@ -11,6 +10,12 @@ Required properties: See ../reset/reset.txt for details. - reset-names: Must be "phy" +Required properties for legacy PHY mode (deprecated): + - #phy-cells: must be 0 + +Required properties for per-lane PHY mode (preferred): + - #phy-cells: must be 1 + Example: grf: syscon@ff770000 {