From patchwork Wed Jul 19 09:57:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9851081 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DA68B60392 for ; Wed, 19 Jul 2017 09:58:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C0B4625F3E for ; Wed, 19 Jul 2017 09:58:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B568C28634; Wed, 19 Jul 2017 09:58:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.9 required=2.0 tests=BAYES_00, RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_DNSWL_HI, RCVD_IN_SBL, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 39CF528632 for ; Wed, 19 Jul 2017 09:58:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753094AbdGSJ6h (ORCPT ); Wed, 19 Jul 2017 05:58:37 -0400 Received: from lucky1.263xmail.com ([211.157.147.132]:39313 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752858AbdGSJ6f (ORCPT ); Wed, 19 Jul 2017 05:58:35 -0400 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.76]) by lucky1.263xmail.com (Postfix) with ESMTP id DEFA564401; Wed, 19 Jul 2017 17:58:15 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id CEE913BF; Wed, 19 Jul 2017 17:58:14 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: kishon@ti.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <4a894fce96b12180849cecc53c65bb6b> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 31903EM8XHI; Wed, 19 Jul 2017 17:58:16 +0800 (CST) From: Shawn Lin To: Kishon Vijay Abraham I , Bjorn Helgaas Cc: Rob Herring , Heiko Stuebner , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Brian Norris , Jeffy Chen , Shawn Lin Subject: [PATCH v5 5/7] arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339 Date: Wed, 19 Jul 2017 17:57:56 +0800 Message-Id: <1500458278-203082-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500458118-139042-1-git-send-email-shawn.lin@rock-chips.com> References: <1500458118-139042-1-git-send-email-shawn.lin@rock-chips.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Convert all RK3399 platforms to use per-lane PHY model in order to save more power by idling the unused lane(s). Signed-off-by: Shawn Lin Reviewed-by: Brian Norris Tested-by: Jeffy Chen --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 69c56f7..5b78ce1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -238,8 +238,10 @@ linux,pci-domain = <0>; max-link-speed = <1>; msi-map = <0x0 &its 0x0 0x1000>; - phys = <&pcie_phy>; - phy-names = "pcie-phy"; + phys = <&pcie_phy 0>, <&pcie_phy 1>, + <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", + "pcie-phy-2", "pcie-phy-3"; ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, @@ -1295,7 +1297,7 @@ compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; - #phy-cells = <0>; + #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; reset-names = "phy"; status = "disabled";