From patchwork Mon Aug 21 15:58:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oza Pawandeep X-Patchwork-Id: 9913101 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6C962602D8 for ; Mon, 21 Aug 2017 15:59:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6534E287AF for ; Mon, 21 Aug 2017 15:59:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 585DE287B3; Mon, 21 Aug 2017 15:59:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_HI,RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EBAF1287AF for ; Mon, 21 Aug 2017 15:59:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932173AbdHUP7A (ORCPT ); Mon, 21 Aug 2017 11:59:00 -0400 Received: from mail-qt0-f171.google.com ([209.85.216.171]:37316 "EHLO mail-qt0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754412AbdHUP64 (ORCPT ); Mon, 21 Aug 2017 11:58:56 -0400 Received: by mail-qt0-f171.google.com with SMTP id 16so84563124qtz.4 for ; Mon, 21 Aug 2017 08:58:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=RJQeO0kxUpiza689MYG0rWiu4rLHZHy/w5hW144+tD4=; b=QhXMND5WssjYj52UvBu+PGA8j0XVthaRq6ip/RHsNyqOQaeT6Cc2HKZKkr9F72yfsX X990BarbzlBSa5eJBTpWwUZWRCt7bGlIdwEkLCngKvzFBX4O7+Cq9SOiOEnOCoGNLo28 fU2fzzMjR+a6nIduo7AcTklLZ2iYiR+kH54As= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=RJQeO0kxUpiza689MYG0rWiu4rLHZHy/w5hW144+tD4=; b=M+nfX70qwHc+kX5nRBewhx1M0mkJT+X0px21XnAc/T2Ab+ruN9x8w55C9jvJOC9jk1 ++ZMznlCtYbjGhOZjzjaN8arTQXAicHSpVIGoh8TYutLHaqGzzqCJxw6R28F9qXbDm+g REXGoefleLkA6Qq6Cs2wKGgabMQt9fU1wcAhU3vdnHiQjzrxe7r1Uc3B+Qb1maAaoH2L 33+fjL2wU5lgoFiV2wW6cbsGMaCHGmlqRLDELxYRpz+PEF1mgLzcNBDI5BX1tvLUzbYC 8/Ns7Nd9JGQoUMoBd09eVNoDlwLtnGYw+TcKUTRaw8fcuqL7MSP4RCi5RIxvfQKuHfJs 1ceg== X-Gm-Message-State: AHYfb5jitjTuvZWjinNq/jqi3cqgZwMDrZIFt2xNrNt7rIpmDETwgKaj Cde89w25LDZpx2EJ X-Received: by 10.200.37.139 with SMTP id e11mr26420354qte.50.1503331135403; Mon, 21 Aug 2017 08:58:55 -0700 (PDT) Received: from anjanavk-OptiPlex-7010.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id p40sm8787217qtp.95.2017.08.21.08.58.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Aug 2017 08:58:54 -0700 (PDT) From: Oza Pawandeep To: Bjorn Helgaas , , Rob Herring , Mark Rutland , Ray Jui , Scott Branden , Jon Mason , bcm-kernel-feedback-list@broadcom.com, Oza Pawandeep , Andy Gospodarek , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Oza Pawandeep Subject: [PATCH v7 2/2] PCI: iproc: add device shutdown for PCI RC Date: Mon, 21 Aug 2017 21:28:44 +0530 Message-Id: <1503331124-25029-3-git-send-email-oza.oza@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1503331124-25029-1-git-send-email-oza.oza@broadcom.com> References: <1503331124-25029-1-git-send-email-oza.oza@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PERST must be asserted around ~500ms before the reboot is applied. During soft reset (e.g., "reboot" from Linux) on some iproc based SOCs LCPLL clock and PERST both goes off simultaneously. This will cause certain Endpoints Intel NVMe not get detected, upon next boot sequence. This is specifically happening with Intel P3700 400GB series. Endpoint is expecting the clock for some amount of time after PERST is asserted, which is not happening in Stingray (iproc based SOC). This causes NVMe to behave in undefined way. On the contrary, Intel x86 boards will have ref clock running, so we do not see this behavior there. Besides, PCI spec does not stipulate about such timings. In-fact it does not tell us, whether PCIe device should consider refclk to be available or not to be. It is completely up to vendor to design their EP the way they want with respect to ref clock availability. 500ms is just based on the observation and taken as safe margin. This patch adds platform shutdown where it should be called in device_shutdown while reboot command is issued. So in sequence first Endpoint Shutdown (e.g. nvme_shutdown) followed by RC shutdown, which issues safe PERST assertion. Signed-off-by: Oza Pawandeep Reviewed-by: Ray Jui Reviewed-by: Scott Branden diff --git a/drivers/pci/host/pcie-iproc-platform.c b/drivers/pci/host/pcie-iproc-platform.c index 2253119..a5073a9 100644 --- a/drivers/pci/host/pcie-iproc-platform.c +++ b/drivers/pci/host/pcie-iproc-platform.c @@ -134,6 +134,13 @@ static int iproc_pcie_pltfm_remove(struct platform_device *pdev) return iproc_pcie_remove(pcie); } +static void iproc_pcie_pltfm_shutdown(struct platform_device *pdev) +{ + struct iproc_pcie *pcie = platform_get_drvdata(pdev); + + iproc_pcie_shutdown(pcie); +} + static struct platform_driver iproc_pcie_pltfm_driver = { .driver = { .name = "iproc-pcie", @@ -141,6 +148,7 @@ static int iproc_pcie_pltfm_remove(struct platform_device *pdev) }, .probe = iproc_pcie_pltfm_probe, .remove = iproc_pcie_pltfm_remove, + .shutdown = iproc_pcie_pltfm_shutdown, }; module_platform_driver(iproc_pcie_pltfm_driver); diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c index a3edae4..7c1b809 100644 --- a/drivers/pci/host/pcie-iproc.c +++ b/drivers/pci/host/pcie-iproc.c @@ -659,7 +659,7 @@ static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn, .write = iproc_pcie_config_write32, }; -static void iproc_pcie_reset(struct iproc_pcie *pcie) +static void iproc_pcie_perst_ctrl(struct iproc_pcie *pcie, bool assert) { u32 val; @@ -671,19 +671,26 @@ static void iproc_pcie_reset(struct iproc_pcie *pcie) if (pcie->ep_is_internal) return; - /* - * Select perst_b signal as reset source. Put the device into reset, - * and then bring it out of reset - */ - val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); - val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST & - ~RC_PCIE_RST_OUTPUT; - iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); - udelay(250); - - val |= RC_PCIE_RST_OUTPUT; - iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); - msleep(100); + if (assert) { + val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); + val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST & + ~RC_PCIE_RST_OUTPUT; + iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); + udelay(250); + } else { + val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); + val |= RC_PCIE_RST_OUTPUT; + iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); + msleep(100); + } +} + +int iproc_pcie_shutdown(struct iproc_pcie *pcie) +{ + iproc_pcie_perst_ctrl(pcie, true); + msleep(500); + + return 0; } static int iproc_pcie_check_link(struct iproc_pcie *pcie) @@ -1365,7 +1372,8 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) goto err_exit_phy; } - iproc_pcie_reset(pcie); + iproc_pcie_perst_ctrl(pcie, true); + iproc_pcie_perst_ctrl(pcie, false); if (pcie->need_ob_cfg) { ret = iproc_pcie_map_ranges(pcie, res); diff --git a/drivers/pci/host/pcie-iproc.h b/drivers/pci/host/pcie-iproc.h index 0bbe2ea..a6b55ce 100644 --- a/drivers/pci/host/pcie-iproc.h +++ b/drivers/pci/host/pcie-iproc.h @@ -110,6 +110,7 @@ struct iproc_pcie { int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res); int iproc_pcie_remove(struct iproc_pcie *pcie); +int iproc_pcie_shutdown(struct iproc_pcie *pcie); #ifdef CONFIG_PCIE_IPROC_MSI int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node);