From patchwork Wed Nov 22 22:49:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Kaya X-Patchwork-Id: 10071629 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7B88A60353 for ; Wed, 22 Nov 2017 22:51:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6EA3229A65 for ; Wed, 22 Nov 2017 22:51:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 638A129E20; Wed, 22 Nov 2017 22:51:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D943529A65 for ; Wed, 22 Nov 2017 22:51:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753293AbdKVWu4 (ORCPT ); Wed, 22 Nov 2017 17:50:56 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:45904 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753350AbdKVWuv (ORCPT ); Wed, 22 Nov 2017 17:50:51 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8523C60BB2; Wed, 22 Nov 2017 22:50:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1511391050; bh=G3kOJZCzL7WkQovoSUcGrXn9M4FDxDl8rr+yf1DLZL8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WO15kHbU/Px2Sp3UaGEot2Tzd0NE014HiTMovIxNiLzofAx8O/NsHdhYb4L91cJb/ PTs0cWTCMxx4aNSglDgLubS8PPF/FPdaCTi08WO+SyUhAVfrTnKFQy7rLaCJrMf6lL wAh1hKalRSKRsOi8g2+nX3g+y+vQ1WoQTm4DxnTw= Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id BE4A860BB0; Wed, 22 Nov 2017 22:50:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1511391047; bh=G3kOJZCzL7WkQovoSUcGrXn9M4FDxDl8rr+yf1DLZL8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eCZ+JEa9bxencyXTNqY9YfRIZbrcXjExS3Jx+rW7cJUdK52wReb3QSEuD697PtxB6 92wb1JTKFY4QEqgdiJ1nDeBPUZhnPMIyjn9GwmY1RYzqe+T6eG9X/hKam71VFMHEgd xL1CI8lm0TKHcYzR8dteKa10MTnfih1o2B6gVXuM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BE4A860BB0 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: linux-pci@vger.kernel.org, timur@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , Antonino Daplas , Bartlomiej Zolnierkiewicz , linux-fbdev@vger.kernel.org (open list:NVIDIA (rivafb and nvidiafb) FRAMEBUFFER DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH V2 27/29] video: fbdev: riva: deprecate pci_get_bus_and_slot() Date: Wed, 22 Nov 2017 17:49:22 -0500 Message-Id: <1511390964-9979-28-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1511390964-9979-1-git-send-email-okaya@codeaurora.org> References: <1511390964-9979-1-git-send-email-okaya@codeaurora.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as where a PCI device is present. This restricts the device drivers to be reused for other domain numbers. Getting ready to remove pci_get_bus_and_slot() function in favor of pci_get_domain_bus_and_slot(). struct riva_par has a pointer to struct pci_dev. Use the pci_dev member to extract the domain information. Change the function signature for CalcStateExt and RivaGetConfig to pass in struct pci_dev in addition to RIVA_HW_INST so that code inside the riva_hw.c can also calculate domain number and pass it to pci_get_domain_bus_and_slot(). Signed-off-by: Sinan Kaya --- drivers/video/fbdev/riva/fbdev.c | 2 +- drivers/video/fbdev/riva/nv_driver.c | 7 ++++--- drivers/video/fbdev/riva/riva_hw.c | 20 +++++++++++++------- drivers/video/fbdev/riva/riva_hw.h | 3 ++- 4 files changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/video/fbdev/riva/fbdev.c b/drivers/video/fbdev/riva/fbdev.c index 1ea78bb..ff82823 100644 --- a/drivers/video/fbdev/riva/fbdev.c +++ b/drivers/video/fbdev/riva/fbdev.c @@ -780,7 +780,7 @@ static int riva_load_video_mode(struct fb_info *info) else newmode.misc_output |= 0x80; - rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width, + rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width, hDisplaySize, height, dotClock); if (rc) goto out; diff --git a/drivers/video/fbdev/riva/nv_driver.c b/drivers/video/fbdev/riva/nv_driver.c index f3694cf..e8e85c1 100644 --- a/drivers/video/fbdev/riva/nv_driver.c +++ b/drivers/video/fbdev/riva/nv_driver.c @@ -159,6 +159,7 @@ unsigned long riva_get_memlen(struct riva_par *par) unsigned int chipset = par->Chipset; struct pci_dev* dev; u32 amt; + u32 domain = pci_domain_nr(par->pdev->bus); switch (chip->Architecture) { case NV_ARCH_03: @@ -226,12 +227,12 @@ unsigned long riva_get_memlen(struct riva_par *par) case NV_ARCH_30: if(chipset == NV_CHIP_IGEFORCE2) { - dev = pci_get_bus_and_slot(0, 1); + dev = pci_get_domain_bus_and_slot(domain, 0, 1); pci_read_config_dword(dev, 0x7C, &amt); pci_dev_put(dev); memlen = (((amt >> 6) & 31) + 1) * 1024; } else if (chipset == NV_CHIP_0x01F0) { - dev = pci_get_bus_and_slot(0, 1); + dev = pci_get_domain_bus_and_slot(domain, 0, 1); pci_read_config_dword(dev, 0x84, &amt); pci_dev_put(dev); memlen = (((amt >> 4) & 127) + 1) * 1024; @@ -417,6 +418,6 @@ unsigned long riva_get_maxdclk(struct riva_par *par) } par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE; - RivaGetConfig(&par->riva, par->Chipset); + RivaGetConfig(&par->riva, par->pdev, par->Chipset); } diff --git a/drivers/video/fbdev/riva/riva_hw.c b/drivers/video/fbdev/riva/riva_hw.c index 8bdf37f..f42e658 100644 --- a/drivers/video/fbdev/riva/riva_hw.c +++ b/drivers/video/fbdev/riva/riva_hw.c @@ -1108,7 +1108,8 @@ static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_ar unsigned pixelDepth, unsigned *burst, unsigned *lwm, - RIVA_HW_INST *chip + RIVA_HW_INST *chip, + struct pci_dev *pdev ) { nv10_fifo_info fifo_data; @@ -1116,8 +1117,9 @@ static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_ar unsigned int M, N, P, pll, MClk, NVClk; unsigned int uMClkPostDiv; struct pci_dev *dev; + u32 domain = pci_domain_nr(pdev->bus); - dev = pci_get_bus_and_slot(0, 3); + dev = pci_get_domain_bus_and_slot(domain, 0, 3); pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); pci_dev_put(dev); uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; @@ -1132,7 +1134,7 @@ static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_ar sim_data.enable_video = 0; sim_data.enable_mp = 0; - dev = pci_get_bus_and_slot(0, 1); + dev = pci_get_domain_bus_and_slot(domain, 0, 1); pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); pci_dev_put(dev); sim_data.memory_type = (sim_data.memory_type >> 12) & 1; @@ -1234,6 +1236,7 @@ static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_ar ( RIVA_HW_INST *chip, RIVA_HW_STATE *state, + struct pci_dev *pdev, int bpp, int width, int hDisplaySize, @@ -1300,7 +1303,7 @@ static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_ar pixelDepth * 8, &(state->arbitration0), &(state->arbitration1), - chip); + chip, pdev); } else { nv10UpdateArbitrationSettings(VClk, pixelDepth * 8, @@ -2102,10 +2105,12 @@ static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_ar static void nv10GetConfig ( RIVA_HW_INST *chip, + struct pci_dev *pdev, unsigned int chipset ) { struct pci_dev* dev; + u32 domain = pci_domain_nr(pdev->bus); u32 amt; #ifdef __BIG_ENDIAN @@ -2118,12 +2123,12 @@ static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_ar * Fill in chip configuration. */ if(chipset == NV_CHIP_IGEFORCE2) { - dev = pci_get_bus_and_slot(0, 1); + dev = pci_get_domain_bus_and_slot(domain, 0, 1); pci_read_config_dword(dev, 0x7C, &amt); pci_dev_put(dev); chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; } else if(chipset == NV_CHIP_0x01F0) { - dev = pci_get_bus_and_slot(0, 1); + dev = pci_get_domain_bus_and_slot(domain, 0, 1); pci_read_config_dword(dev, 0x84, &amt); pci_dev_put(dev); chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; @@ -2224,6 +2229,7 @@ static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_ar int RivaGetConfig ( RIVA_HW_INST *chip, + struct pci_dev *pdev, unsigned int chipset ) { @@ -2245,7 +2251,7 @@ static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_ar case NV_ARCH_10: case NV_ARCH_20: case NV_ARCH_30: - nv10GetConfig(chip, chipset); + nv10GetConfig(chip, pdev, chipset); break; default: return (-1); diff --git a/drivers/video/fbdev/riva/riva_hw.h b/drivers/video/fbdev/riva/riva_hw.h index c2769f7..5e7b354 100644 --- a/drivers/video/fbdev/riva/riva_hw.h +++ b/drivers/video/fbdev/riva/riva_hw.h @@ -536,6 +536,7 @@ ( RIVA_HW_INST *chip, RIVA_HW_STATE *state, + struct pci_dev *pdev, int bpp, int width, int hDisplaySize, @@ -546,7 +547,7 @@ /* * External routines. */ -int RivaGetConfig(RIVA_HW_INST *, unsigned int); +int RivaGetConfig(RIVA_HW_INST *chip, struct pci_dev *pdev, unsigned int c); /* * FIFO Free Count. Should attempt to yield processor if RIVA is busy. */