From patchwork Wed Dec 20 02:52:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honghui Zhang X-Patchwork-Id: 10124825 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C992E6057F for ; Wed, 20 Dec 2017 02:52:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C355929436 for ; Wed, 20 Dec 2017 02:52:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B7DA329470; Wed, 20 Dec 2017 02:52:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 36BC829436 for ; Wed, 20 Dec 2017 02:52:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753583AbdLTCwX (ORCPT ); Tue, 19 Dec 2017 21:52:23 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:33799 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751559AbdLTCwW (ORCPT ); Tue, 19 Dec 2017 21:52:22 -0500 X-UUID: f774c4d34eef44e08ac9145a70fbf58f-20171220 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2116578516; Wed, 20 Dec 2017 10:52:19 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 20 Dec 2017 10:52:17 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 20 Dec 2017 10:52:17 +0800 From: To: , , , , , , , , , CC: , , , , , , Subject: [PATCH] PCI: Mediatek: clear irq status after irq dispathed to avoid reentry Date: Wed, 20 Dec 2017 10:52:14 +0800 Message-ID: <1513738334-26213-1-git-send-email-honghui.zhang@mediatek.com> X-Mailer: git-send-email 2.6.4 MIME-Version: 1.0 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Honghui Zhang There maybe a same irq reentry scenario after irq received in current irq handle flow: EP device PCIe host driver EP driver 1. issue an irq 2. received irq 3. clear irq status 4. dispatch irq 5. clear irq source The irq status was not successfully cleared at step 2 since the irq source was not cleared yet. So the PCIe host driver may receive the same irq after step 5. Then there's an irq reentry occurred. Even worse, if the reentry irq was not an irq that EP driver expected, it may not handle the irq. Then we may run into the dead loop from step 2 to step 4. Clear the irq status after irq have been dispatched to avoid the irq reentry. Signed-off-by: Honghui Zhang Acked-by: Ryder Lee --- drivers/pci/host/pcie-mediatek.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c index db93efd..3248771 100644 --- a/drivers/pci/host/pcie-mediatek.c +++ b/drivers/pci/host/pcie-mediatek.c @@ -605,11 +605,11 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data) while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) { for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { - /* Clear the INTx */ - writel(1 << bit, port->base + PCIE_INT_STATUS); virq = irq_find_mapping(port->irq_domain, bit - INTX_SHIFT); generic_handle_irq(virq); + /* Clear the INTx */ + writel(1 << bit, port->base + PCIE_INT_STATUS); } } @@ -619,10 +619,10 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data) while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) { - /* Clear the MSI */ - writel(1 << bit, port->base + PCIE_IMSI_STATUS); virq = irq_find_mapping(port->msi_domain, bit); generic_handle_irq(virq); + /* Clear the MSI */ + writel(1 << bit, port->base + PCIE_IMSI_STATUS); } } /* Clear MSI interrupt status */