From patchwork Wed Dec 27 00:59:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honghui Zhang X-Patchwork-Id: 10133307 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 569066037D for ; Wed, 27 Dec 2017 01:00:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A4AD2C61A for ; Wed, 27 Dec 2017 01:00:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3ED0E2C71A; Wed, 27 Dec 2017 01:00:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C443A2C61A for ; Wed, 27 Dec 2017 01:00:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751716AbdL0BA3 (ORCPT ); Tue, 26 Dec 2017 20:00:29 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:46018 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751278AbdL0BAF (ORCPT ); Tue, 26 Dec 2017 20:00:05 -0500 X-UUID: 8cddcd8bfebc446e888ebb4b924d8bbf-20171227 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 276545362; Wed, 27 Dec 2017 09:00:02 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 27 Dec 2017 08:59:59 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 27 Dec 2017 08:59:58 +0800 From: To: , , , , , , , , , , CC: , , , , , , Subject: [PATCH v5 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622 Date: Wed, 27 Dec 2017 08:59:54 +0800 Message-ID: <1514336394-17747-3-git-send-email-honghui.zhang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1514336394-17747-1-git-send-email-honghui.zhang@mediatek.com> References: <1514336394-17747-1-git-send-email-honghui.zhang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Honghui Zhang The hardware default value of IDs and class type is not correct, fix that by setup the correct values before start up. Signed-off-by: Honghui Zhang --- drivers/pci/host/pcie-mediatek.c | 12 ++++++++++++ include/linux/pci_ids.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c index fc29a9a..62aac0ea 100644 --- a/drivers/pci/host/pcie-mediatek.c +++ b/drivers/pci/host/pcie-mediatek.c @@ -74,6 +74,10 @@ /* PCIe V2 per-port registers */ #define PCIE_MSI_VECTOR 0x0c0 + +#define PCIE_CONF_ID 0x100 +#define PCIE_CONF_CLASS 0x104 + #define PCIE_INT_MASK 0x420 #define INTX_MASK GENMASK(19, 16) #define INTX_SHIFT 16 @@ -393,6 +397,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val |= PCIE_CSR_LTSSM_EN(port->slot) | PCIE_CSR_ASPM_L1_EN(port->slot); writel(val, pcie->base + PCIE_SYS_CFG_V2); + + /* Set up vendor ID and device ID for MT7622*/ + val = PCI_VENDOR_ID_MEDIATEK; + writel(val, port->base + PCIE_CONF_ID); + + /* Set up class code for MT7622 */ + val = PCI_CLASS_BRIDGE_PCI << 16; + writel(val, port->base + PCIE_CONF_CLASS); } /* Assert all reset signals */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index ab20dc5..2480b0e 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2113,6 +2113,8 @@ #define PCI_VENDOR_ID_MYRICOM 0x14c1 +#define PCI_VENDOR_ID_MEDIATEK 0x14c3 + #define PCI_VENDOR_ID_TITAN 0x14D2 #define PCI_DEVICE_ID_TITAN_010L 0x8001 #define PCI_DEVICE_ID_TITAN_100L 0x8010