From patchwork Fri Mar 30 07:14:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Gilboa X-Patchwork-Id: 10317095 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2C7126063D for ; Fri, 30 Mar 2018 07:15:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 18F102A544 for ; Fri, 30 Mar 2018 07:15:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0DCF42A55A; Fri, 30 Mar 2018 07:15:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 98B772A559 for ; Fri, 30 Mar 2018 07:15:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752626AbeC3HPE (ORCPT ); Fri, 30 Mar 2018 03:15:04 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:33169 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752712AbeC3HPA (ORCPT ); Fri, 30 Mar 2018 03:15:00 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from talgi@mellanox.com) with ESMTPS (AES256-SHA encrypted); 30 Mar 2018 10:15:52 +0300 Received: from gen-l-vrt-178.mtl.labs.mlnx (gen-l-vrt-178.mtl.labs.mlnx [10.137.178.1]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w2U7EuTn008173; Fri, 30 Mar 2018 10:14:56 +0300 Received: from gen-l-vrt-178.mtl.labs.mlnx (localhost [127.0.0.1]) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7) with ESMTP id w2U7EtJq003608; Fri, 30 Mar 2018 10:14:55 +0300 Received: (from talgi@localhost) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7/Submit) id w2U7Et8M003607; Fri, 30 Mar 2018 10:14:55 +0300 From: Tal Gilboa To: Bjorn Helgaas Cc: Linux PCI , Tariq Toukan , Saeed Mahameed , Keller Jacob E , Tal Gilboa Subject: [PATCH next V4 3/8] PCI: Add device link bandwidth capabilities calculation Date: Fri, 30 Mar 2018 10:14:41 +0300 Message-Id: <1522394086-3555-4-git-send-email-talgi@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1522394086-3555-1-git-send-email-talgi@mellanox.com> References: <1522394086-3555-1-git-send-email-talgi@mellanox.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Added a function for calculating a PCI device's total link bandwidth capabilities. This function queries for the device link speed and width, multiplies them and applies encoding overhead for the different PCIe generations. Signed-off-by: Tal Gilboa Reviewed-by: Tariq Toukan --- drivers/pci/pci.c | 22 ++++++++++++++++++++++ include/linux/pci.h | 12 ++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 90a6cf2..553d8f3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5212,6 +5212,28 @@ int pcie_get_width_cap(struct pci_dev *dev, enum pcie_link_width *width) EXPORT_SYMBOL(pcie_get_width_cap); /** + * pcie_bandwidth_capable - Calculates a PCI device's link bandwidth capability + * @dev: PCI device + * @speed: storage for link speed + * @width: storage for link width + * + * This function caculates a PCI device's link bandwidth by querying for its + * link speed and width, multiplying them, and applying encoding overhead. + */ +int pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, + enum pcie_link_width *width) +{ + pcie_get_speed_cap(dev, speed); + pcie_get_width_cap(dev, width); + + if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) + return 0; + + return (*width) * PCIE_SPEED2MBS_ENC(*speed); +} +EXPORT_SYMBOL(pcie_bandwidth_capable); + +/** * pci_select_bars - Make BAR mask from the type of resource * @dev: the PCI device for which BAR mask is made * @flags: resource type mask to be selected diff --git a/include/linux/pci.h b/include/linux/pci.h index 1e3d05f..9f57c45 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -265,6 +265,16 @@ enum pci_bus_speed { (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ "Unknown speed") +/** + * PCIe speed to Mb/s with encoding overhead: + * 20% for gen2, ~1.5% for gen3 + */ +#define PCIE_SPEED2MBS_ENC(speed) \ + ((speed) == PCIE_SPEED_8_0GT ? 7877 : \ + (speed) == PCIE_SPEED_5_0GT ? 4000 : \ + (speed) == PCIE_SPEED_2_5GT ? 2000 : \ + 0) + struct pci_cap_saved_data { u16 cap_nr; bool cap_extended; @@ -1090,6 +1100,8 @@ int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, enum pcie_link_width *width); int pcie_get_speed_cap(struct pci_dev *dev, enum pci_bus_speed *speed); int pcie_get_width_cap(struct pci_dev *dev, enum pcie_link_width *width); +int pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, + enum pcie_link_width *width); void pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev);