From patchwork Fri Mar 30 07:14:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Gilboa X-Patchwork-Id: 10317099 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7429C60383 for ; Fri, 30 Mar 2018 07:15:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5E8AD2A544 for ; Fri, 30 Mar 2018 07:15:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 539E12A55A; Fri, 30 Mar 2018 07:15:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A30922A544 for ; Fri, 30 Mar 2018 07:15:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752824AbeC3HPD (ORCPT ); Fri, 30 Mar 2018 03:15:03 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:33171 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752714AbeC3HPA (ORCPT ); Fri, 30 Mar 2018 03:15:00 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from talgi@mellanox.com) with ESMTPS (AES256-SHA encrypted); 30 Mar 2018 10:15:52 +0300 Received: from gen-l-vrt-178.mtl.labs.mlnx (gen-l-vrt-178.mtl.labs.mlnx [10.137.178.1]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w2U7Eue1008176; Fri, 30 Mar 2018 10:14:56 +0300 Received: from gen-l-vrt-178.mtl.labs.mlnx (localhost [127.0.0.1]) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7) with ESMTP id w2U7EuXX003610; Fri, 30 Mar 2018 10:14:56 +0300 Received: (from talgi@localhost) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7/Submit) id w2U7Euw0003609; Fri, 30 Mar 2018 10:14:56 +0300 From: Tal Gilboa To: Bjorn Helgaas Cc: Linux PCI , Tariq Toukan , Saeed Mahameed , Keller Jacob E , Tal Gilboa Subject: [PATCH next V4 4/8] PCI: Calculate available bandwidth for PCI devices Date: Fri, 30 Mar 2018 10:14:42 +0300 Message-Id: <1522394086-3555-5-git-send-email-talgi@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1522394086-3555-1-git-send-email-talgi@mellanox.com> References: <1522394086-3555-1-git-send-email-talgi@mellanox.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP pcie_bandwidth_available() function, which is based on pcie_get_minimum_link(), iterates over the PCI chain and calculates available bandwidth in addition to minimum speed and width. The bandwidth calculation at each level is encoding * speed * width, so even if, for instance, a level has lower width than the device max capabilities, it still might not cause a bandwidth limitation if it has a higher speed. The function also returns the device causing the limitation. pcie_get_minimum_link() is kept for compatibility. Signed-off-by: Tal Gilboa Reviewed-by: Tariq Toukan --- drivers/pci/pci.c | 45 ++++++++++++++++++++++++++++++++++++++------- include/linux/pci.h | 3 +++ 2 files changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 553d8f3..fb79ff6 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5109,25 +5109,48 @@ int pcie_set_mps(struct pci_dev *dev, int mps) * @speed: storage for minimum speed * @width: storage for minimum width * - * This function will walk up the PCI device chain and determine the minimum - * link width and speed of the device. + * This function use pcie_bandwidth_available() for determining the minimum + * link width and speed of the device. Legacy code is kept for compatibility. */ int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, enum pcie_link_width *width) { - int ret; + int bw; + + return pcie_bandwidth_available(dev, speed, width, &bw, NULL); +} +EXPORT_SYMBOL(pcie_get_minimum_link); + +/** + * pcie_bandwidth_available - determine minimum link settings of a PCIe + device and its bandwidth limitation + * @dev: PCI device to query + * @speed: storage for minimum speed + * @width: storage for minimum width + * @bw: storage for link bandwidth + * @limiting_dev: storage for device causing the bandwidth limitation + * + * This function walks up the PCI device chain and determines the minimum width, + * minimum speed and available bandwidth of the device. + */ +int pcie_bandwidth_available(struct pci_dev *dev, enum pci_bus_speed *speed, + enum pcie_link_width *width, int *bw, + struct pci_dev **limiting_dev) +{ + int err; *speed = PCI_SPEED_UNKNOWN; *width = PCIE_LNK_WIDTH_UNKNOWN; + *bw = 0; while (dev) { u16 lnksta; enum pci_bus_speed next_speed; enum pcie_link_width next_width; - ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); - if (ret) - return ret; + err = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + if (err) + return err; next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> @@ -5139,12 +5162,20 @@ int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, if (next_width < *width) *width = next_width; + /* Check if current device limits the total bandwidth */ + if (!(*bw) || + (*bw > next_width * PCIE_SPEED2MBS_ENC(next_speed))) { + if (limiting_dev) + *limiting_dev = dev; + *bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); + } + dev = dev->bus->self; } return 0; } -EXPORT_SYMBOL(pcie_get_minimum_link); +EXPORT_SYMBOL(pcie_bandwidth_available); /** * pcie_get_speed_cap - queries for the PCI device's link speed capability diff --git a/include/linux/pci.h b/include/linux/pci.h index 9f57c45..585cea1 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1098,6 +1098,9 @@ static inline int pci_is_managed(struct pci_dev *pdev) int pcie_set_mps(struct pci_dev *dev, int mps); int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, enum pcie_link_width *width); +int pcie_bandwidth_available(struct pci_dev *dev, enum pci_bus_speed *speed, + enum pcie_link_width *width, int *bw, + struct pci_dev **limiting_dev); int pcie_get_speed_cap(struct pci_dev *dev, enum pci_bus_speed *speed); int pcie_get_width_cap(struct pci_dev *dev, enum pcie_link_width *width); int pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,