From patchwork Fri Mar 30 07:14:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Gilboa X-Patchwork-Id: 10317103 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B9F82602A7 for ; Fri, 30 Mar 2018 07:15:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A65562A544 for ; Fri, 30 Mar 2018 07:15:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9B35C2A55A; Fri, 30 Mar 2018 07:15:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC1B02A544 for ; Fri, 30 Mar 2018 07:15:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752780AbeC3HPD (ORCPT ); Fri, 30 Mar 2018 03:15:03 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:33191 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752840AbeC3HPA (ORCPT ); Fri, 30 Mar 2018 03:15:00 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from talgi@mellanox.com) with ESMTPS (AES256-SHA encrypted); 30 Mar 2018 10:15:53 +0300 Received: from gen-l-vrt-178.mtl.labs.mlnx (gen-l-vrt-178.mtl.labs.mlnx [10.137.178.1]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w2U7EvYv008188; Fri, 30 Mar 2018 10:14:57 +0300 Received: from gen-l-vrt-178.mtl.labs.mlnx (localhost [127.0.0.1]) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7) with ESMTP id w2U7EvdM003618; Fri, 30 Mar 2018 10:14:57 +0300 Received: (from talgi@localhost) by gen-l-vrt-178.mtl.labs.mlnx (8.14.7/8.14.7/Submit) id w2U7Evmm003617; Fri, 30 Mar 2018 10:14:57 +0300 From: Tal Gilboa To: Bjorn Helgaas Cc: Linux PCI , Tariq Toukan , Saeed Mahameed , Keller Jacob E , Tal Gilboa Subject: [PATCH next V4 8/8] net/mlx5e: Use generic PCI function for bandwidth calculation Date: Fri, 30 Mar 2018 10:14:46 +0300 Message-Id: <1522394086-3555-9-git-send-email-talgi@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1522394086-3555-1-git-send-email-talgi@mellanox.com> References: <1522394086-3555-1-git-send-email-talgi@mellanox.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Newly introduced pci_bandwidth_available() function calculates maximum available bandwidth through the PCI chain. We can use this value for mlx5e_get_pci_bw() instead of calculating ourselves. This is mainly used for detecting cases on which PCIe bandwidth can't support current link speed and the driver need to act accordingly. By taking PCIe encoding into account, this calculation is even more accurate. Signed-off-by: Tal Gilboa Reviewed-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 4a675f1..fc51a73 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -4011,27 +4011,16 @@ static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw) enum pcie_link_width width; enum pci_bus_speed speed; int err = 0; + int bw; - err = pcie_get_minimum_link(mdev->pdev, &speed, &width); + err = pcie_bandwidth_available(mdev->pdev, &speed, &width, &bw, NULL); if (err) return err; if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) return -EINVAL; - switch (speed) { - case PCIE_SPEED_2_5GT: - *pci_bw = 2500 * width; - break; - case PCIE_SPEED_5_0GT: - *pci_bw = 5000 * width; - break; - case PCIE_SPEED_8_0GT: - *pci_bw = 8000 * width; - break; - default: - return -EINVAL; - } + *pci_bw = bw; return 0; }