From patchwork Tue May 29 21:58:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 10437203 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 37839602BF for ; Tue, 29 May 2018 22:00:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2766B2886B for ; Tue, 29 May 2018 22:00:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1BBE8288E8; Tue, 29 May 2018 22:00:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6DFA52886B for ; Tue, 29 May 2018 22:00:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967540AbeE2WAY (ORCPT ); Tue, 29 May 2018 18:00:24 -0400 Received: from mail-qt0-f194.google.com ([209.85.216.194]:45707 "EHLO mail-qt0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967446AbeE2V7I (ORCPT ); Tue, 29 May 2018 17:59:08 -0400 Received: by mail-qt0-f194.google.com with SMTP id i18-v6so10073181qtp.12 for ; Tue, 29 May 2018 14:59:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LLTPzUzIgO+y22OuB/+G/NHvaRPwVL44es7Sno0eJks=; b=cfNVsgJVYHQitZ+AnZNAqCdNJ1MfyqrT//8j7TUoRJc/BCRXJ81v4oykcWiDV8DLyA BFr3V3qF1Dsvy6Dz5KdAsWJ/soVb5Yl7ZI8euf/TEtj3BL1akzmp7H49p2zOB1ALia70 l0YvVrd1QPS/50TUP1x2Sc3wDSCaYKj51ILXQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LLTPzUzIgO+y22OuB/+G/NHvaRPwVL44es7Sno0eJks=; b=djL38zJBoLkMxMMifk2wf6VC8xZtr1ob+odIURwnGab98FVBmqjnqhu6VY7P2Unzap MyyaOW4VUCTzik4cqVY+GxZH8BX3oaXZhmSWDD2ZtVgGavjvAZlsM63x1tnpyhVLiut5 W5kFvbDB7Q55CjsnQeYEeov2Bvl0Fz6oakegPT2v42K2RqVlQmDxnUCV8Ru2i7XvhRa2 UpagRsLodFxk+KybzcmTMbe6VpKzvEOjoDFpBLVQtx5GyQahgYbQ+6gkpgxpad16JEnb AC53cIGv+/Scm/fZS6WnxJG7GCNKiyNXDnxtXUxdcHGjS5T2Pl+hTxxq7i4xLJ1Bxo7q 9Gng== X-Gm-Message-State: APt69E0YXzw3bolXyg/sJBlb57t7tj5w+fnRGppGSPrl+kU5ZV23IZY4 iuqMVyo0L5pUJDQUBP7/XIvspQ== X-Google-Smtp-Source: ADUXVKKFnD6V+GaY3UcruIPThf8oiBUszTgZVzNfAuWoOB05CUNZyCjjx3C64FYVwolE3VWoRKR71g== X-Received: by 2002:a0c:8c0b:: with SMTP id n11-v6mr186035qvb.228.1527631147256; Tue, 29 May 2018 14:59:07 -0700 (PDT) Received: from lbrmn-lnxub44-1.ric.broadcom.com ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id a83-v6sm23217073qkb.22.2018.05.29.14.59.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 May 2018 14:59:06 -0700 (PDT) From: Ray Jui To: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Mark Rutland Cc: linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ray Jui Subject: [PATCH 2/6] PCI: iproc: Add INTx support with better modeling Date: Tue, 29 May 2018 14:58:46 -0700 Message-Id: <1527631130-20045-3-git-send-email-ray.jui@broadcom.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527631130-20045-1-git-send-email-ray.jui@broadcom.com> References: <1527631130-20045-1-git-send-email-ray.jui@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add PCIe legacy interrupt INTx support to the iProc PCIe driver by modeling it with its own IRQ domain. All 4 interrupts INTA, INTB, INTC, INTD share the same interrupt line connected to the GIC in the system, while the status of each INTx can be obtained through the INTX CSR register Signed-off-by: Ray Jui --- drivers/pci/host/pcie-iproc-platform.c | 2 + drivers/pci/host/pcie-iproc.c | 95 +++++++++++++++++++++++++++++++++- drivers/pci/host/pcie-iproc.h | 6 +++ 3 files changed, 101 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pcie-iproc-platform.c b/drivers/pci/host/pcie-iproc-platform.c index e764a2a..7a51e6c 100644 --- a/drivers/pci/host/pcie-iproc-platform.c +++ b/drivers/pci/host/pcie-iproc-platform.c @@ -70,6 +70,8 @@ static int iproc_pcie_pltfm_probe(struct platform_device *pdev) } pcie->base_addr = reg.start; + pcie->irq = platform_get_irq(pdev, 0); + if (of_property_read_bool(np, "brcm,pcie-ob")) { u32 val; diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c index 14f374d..0bd2c14 100644 --- a/drivers/pci/host/pcie-iproc.c +++ b/drivers/pci/host/pcie-iproc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -264,6 +265,7 @@ enum iproc_pcie_reg { /* enable INTx */ IPROC_PCIE_INTX_EN, + IPROC_PCIE_INTX_CSR, /* outbound address mapping */ IPROC_PCIE_OARR0, @@ -305,6 +307,7 @@ static const u16 iproc_pcie_reg_paxb_bcma[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_LINK_STATUS] = 0xf0c, }; @@ -316,6 +319,7 @@ static const u16 iproc_pcie_reg_paxb[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_OARR0] = 0xd20, [IPROC_PCIE_OMAP0] = 0xd40, [IPROC_PCIE_OARR1] = 0xd28, @@ -332,6 +336,7 @@ static const u16 iproc_pcie_reg_paxb_v2[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_OARR0] = 0xd20, [IPROC_PCIE_OMAP0] = 0xd40, [IPROC_PCIE_OARR1] = 0xd28, @@ -782,9 +787,90 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) return link_is_active ? 0 : -ENODEV; } -static void iproc_pcie_enable(struct iproc_pcie *pcie) +static int iproc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) { + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops = { + .map = iproc_pcie_intx_map, +}; + +static void iproc_pcie_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct iproc_pcie *pcie; + struct device *dev; + unsigned long status; + u32 bit, virq; + + chained_irq_enter(chip, desc); + pcie = irq_desc_get_handler_data(desc); + dev = pcie->dev; + + /* go through INTx A, B, C, D until all interrupts are handled */ + while ((status = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_CSR) & + SYS_RC_INTX_MASK) != 0) { + for_each_set_bit(bit, &status, PCI_NUM_INTX) { + virq = irq_find_mapping(pcie->irq_domain, bit + 1); + if (virq) + generic_handle_irq(virq); + else + dev_err(dev, "unexpected INTx%u\n", bit); + } + } + + chained_irq_exit(chip, desc); +} + +static int iproc_pcie_intx_enable(struct iproc_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *node = dev->of_node; + int ret; + iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); + + /* + * BCMA devices do not map INTx the same way as platform devices. All + * BCMA needs is the above code to enable INTx + */ + if (pcie->irq <= 0) + return 0; + + /* set IRQ handler */ + irq_set_chained_handler_and_data(pcie->irq, iproc_pcie_isr, pcie); + + /* add IRQ domain for INTx */ + pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX + 1, + &intx_domain_ops, pcie); + if (!pcie->irq_domain) { + dev_err(dev, "failed to add INTx IRQ domain\n"); + ret = -ENOMEM; + goto err_rm_handler_data; + } + + return 0; + +err_rm_handler_data: + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); + + return ret; +} + +static void iproc_pcie_intx_disable(struct iproc_pcie *pcie) +{ + iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, 0x0); + + if (pcie->irq <= 0) + return; + + irq_domain_remove(pcie->irq_domain); + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); } static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie, @@ -1410,7 +1496,11 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) goto err_power_off_phy; } - iproc_pcie_enable(pcie); + ret = iproc_pcie_intx_enable(pcie); + if (ret) { + dev_err(dev, "failed to enable INTx\n"); + goto err_power_off_phy; + } if (IS_ENABLED(CONFIG_PCI_MSI)) if (iproc_pcie_msi_enable(pcie)) @@ -1455,6 +1545,7 @@ int iproc_pcie_remove(struct iproc_pcie *pcie) pci_remove_root_bus(pcie->root_bus); iproc_pcie_msi_disable(pcie); + iproc_pcie_intx_disable(pcie); phy_power_off(pcie->phy); phy_exit(pcie->phy); diff --git a/drivers/pci/host/pcie-iproc.h b/drivers/pci/host/pcie-iproc.h index 67081cb..cbcaf9d 100644 --- a/drivers/pci/host/pcie-iproc.h +++ b/drivers/pci/host/pcie-iproc.h @@ -72,6 +72,9 @@ struct iproc_msi; * @ib: inbound mapping related parameters * @ib_map: outbound mapping region related parameters * + * @irq: interrupt line wired to the generic GIC for INTx + * @irq_domain: IRQ domain for INTx + * * @need_msi_steer: indicates additional configuration of the iProc PCIe * controller is required to steer MSI writes to external interrupt controller * @msi: MSI data @@ -99,6 +102,9 @@ struct iproc_pcie { struct iproc_pcie_ib ib; const struct iproc_pcie_ib_map *ib_map; + int irq; + struct irq_domain *irq_domain; + bool need_msi_steer; struct iproc_msi *msi; };