From patchwork Wed Sep 19 14:31:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 10605937 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E4046CB for ; Wed, 19 Sep 2018 14:33:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D91F92AF25 for ; Wed, 19 Sep 2018 14:33:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CCBF22B457; Wed, 19 Sep 2018 14:33:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B5692AF25 for ; Wed, 19 Sep 2018 14:33:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731576AbeISULJ (ORCPT ); Wed, 19 Sep 2018 16:11:09 -0400 Received: from mail-qt0-f195.google.com ([209.85.216.195]:46956 "EHLO mail-qt0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728096AbeISULJ (ORCPT ); Wed, 19 Sep 2018 16:11:09 -0400 Received: by mail-qt0-f195.google.com with SMTP id l42-v6so5237310qtf.13; Wed, 19 Sep 2018 07:32:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TLBiLM1mdu1HxR4W2fQf8NiJqsLvqjL8vfP6p3vMZ+w=; b=WZ53WoKUusbA3cHPVmaeu4I1DvIcIOmtdV6PfCRnqSjYtDObuE+Nc3N8sx1V8uR1q5 /H/QAyXcWy3qRXdZ75wF2Od3gQHruAFvmPtPkpv+fCAwrczKJJz1yOXvjxXKToqlc/0+ 0OJ+csAnhvOvsPJz8iooWn5QDryrutjo9HBXK/k5WBSwDJAqNhjoXPQaG3N4nTcVxMJL JHthiMRJ6DttM5KBJBSbnpP5casJ8yqZ5ZwKB3IDmHDniokiP0/LX/EiY8hzFWWVPdDR fVURdenDFXnF/loyldrY4bnyXkpNvDCYxcRKGvFM66Fvoq7LnmNY09Bfe+maOQr1WIhZ 4xNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TLBiLM1mdu1HxR4W2fQf8NiJqsLvqjL8vfP6p3vMZ+w=; b=XWFjraTVHkF/6wi5trBvQ6zWYwb+bfT0qMO9uVJKGAJev2L5qyaZ49d8CI+Lt/JpkG /HqYuvD0ZsrsXje0O/l5E9b8eieHEIB9Fo+QsWfAJZLOIzvBegCYSosDU8mG17iTs6UC b1wa/+GBeeWR0cbiFSp0UOysAgP55byNWkClERpNI1QRCiHJSMhDZs4fU9XQarDzOPRt aA4KyW3tcJpCaQLAb1ywbGWGNdAqiiOgpSI5e/wbUPhl841Iw/ZR70dfoHjYvP8Eyqp3 ti03ltRukQUOQXk0C7+8GymdRnLFL0npFwGMzFdijE1Gty10xUZNzDHsbAnBZy/k6mGf /BmQ== X-Gm-Message-State: APzg51AleskXavr5TLF/Uwpbs73AOqJxZkJ1fOD/QtpNChnmOj4b4V+2 g+vzeIeiJ+h279Sy47Cv2Fg78uxt X-Google-Smtp-Source: ANB0Vdaoy/bMUe/Yab81ePa9h/gnrBVobMUqYgkmgHWY15T0tkCpyngXC68ZnraC7jDlxqOqgBwqHA== X-Received: by 2002:ac8:1bf6:: with SMTP id m51-v6mr23892699qtk.143.1537367576468; Wed, 19 Sep 2018 07:32:56 -0700 (PDT) Received: from stbsrv-and-3.and.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id 17-v6sm2104051qkf.74.2018.09.19.07.32.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Sep 2018 07:32:55 -0700 (PDT) From: Jim Quinlan To: linux-kernel@vger.kernel.org Cc: Jim Quinlan , Bjorn Helgaas , Rob Herring , Mark Rutland , Brian Norris , Gregory Fong , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Christoph Hellwig Subject: [PATCH v5 02/12] dt-bindings: pci: add DT docs for Brcmstb PCIe device Date: Wed, 19 Sep 2018 10:31:57 -0400 Message-Id: <1537367527-20773-3-git-send-email-jim2101024@gmail.com> X-Mailer: git-send-email 1.9.0.138.g2de3478 In-Reply-To: <1537367527-20773-1-git-send-email-jim2101024@gmail.com> References: <1537367527-20773-1-git-send-email-jim2101024@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DT bindings description of the Brcmstb PCIe device is described. This node can be used by almost all Broadcom settop box chips, using ARM, ARM64, or MIPS CPU architectures. Signed-off-by: Jim Quinlan Acked-by: Rob Herring --- .../devicetree/bindings/pci/brcmstb-pcie.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt new file mode 100644 index 0000000..a1a9ad5 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt @@ -0,0 +1,59 @@ +Brcmstb PCIe Host Controller Device Tree Bindings + +Required Properties: +- compatible + "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs. + "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs. + "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including + the 7278). + "brcm,bcm7278-pcie" -- for 7278 family ARM-based SOCs. + +- reg -- the register start address and length for the PCIe reg block. +- interrupts -- two interrupts are specified; the first interrupt is for + the PCI host controller and the second is for MSI if the built-in + MSI controller is to be used. +- interrupt-names -- names of the interrupts (above): "pcie" and "msi". +- #address-cells -- set to <3>. +- #size-cells -- set to <2>. +- #interrupt-cells: set to <1>. +- interrupt-map-mask and interrupt-map, standard PCI properties to define the + mapping of the PCIe interface to interrupt numbers. +- ranges: ranges for the PCI memory and I/O regions. +- linux,pci-domain -- should be unique per host controller. + +Optional Properties: +- clocks -- phandle of pcie clock. +- clock-names -- set to "sw_pcie" if clocks is used. +- dma-ranges -- Specifies the inbound memory mapping regions when + an "identity map" is not possible. +- msi-controller -- this property is typically specified to have the + PCIe controller use its internal MSI controller. +- msi-parent -- set to use an external MSI interrupt controller. +- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking. +- max-link-speed -- (integer) indicates desired generation of link: + 1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3). + +Example Node: + +pcie0: pcie@f0460000 { + reg = <0x0 0xf0460000 0x0 0x9310>; + interrupts = <0x0 0x0 0x4>; + compatible = "brcm,bcm7445-pcie"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000 + 0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc 0 47 3 + 0 0 0 2 &intc 0 48 3 + 0 0 0 3 &intc 0 49 3 + 0 0 0 4 &intc 0 50 3>; + clocks = <&sw_pcie0>; + clock-names = "sw_pcie"; + msi-parent = <&pcie0>; /* use PCIe's internal MSI controller */ + msi-controller; /* use PCIe's internal MSI controller */ + brcm,ssc; + max-link-speed = <1>; + linux,pci-domain = <0>; + };