From patchwork Thu Dec 13 20:21:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10729793 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D2CF86C5 for ; Thu, 13 Dec 2018 20:21:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C7DB22CAB6 for ; Thu, 13 Dec 2018 20:21:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BC0AB2CACE; Thu, 13 Dec 2018 20:21:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 713802CAB6 for ; Thu, 13 Dec 2018 20:21:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726630AbeLMUVs (ORCPT ); Thu, 13 Dec 2018 15:21:48 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:2262 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726408AbeLMUVs (ORCPT ); Thu, 13 Dec 2018 15:21:48 -0500 X-IronPort-AV: E=Sophos;i="5.56,349,1539615600"; d="scan'208";a="2765902" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 Dec 2018 05:21:45 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.37.69]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4363B4072C4F; Fri, 14 Dec 2018 05:21:43 +0900 (JST) From: Fabrizio Castro To: Rob Herring , Mark Rutland Cc: Fabrizio Castro , Bjorn Helgaas , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Simon Horman , Geert Uytterhoeven , Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH] dt-bindings: PCI: rcar: Add device tree support for r8a774c0 Date: Thu, 13 Dec 2018 20:21:40 +0000 Message-Id: <1544732500-6866-1-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add PCIe support for the RZ/G2E (a.k.a. R8A774C0). Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/pci/rcar-pci.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt index 976ef7b..bb89fed 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -3,6 +3,7 @@ Required properties: compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a7744" for the R8A7744 SoC; + "renesas,pcie-r8a774c0" for the R8A774C0 SoC; "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7790" for the R8A7790 SoC; "renesas,pcie-r8a7791" for the R8A7791 SoC; @@ -13,7 +14,8 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a77990" for the R8A77990 SoC; "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or RZ/G1 compatible device. - "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device. + "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or + RZ/G2 compatible device. When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first @@ -37,7 +39,8 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; Optional properties: - phys: from common PHY binding: PHY phandle and specifier (only make sense - for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks). + for R-Car gen3 and RZ/G2 SoCs where the PCIe PHYs have their own + register blocks). - phy-names: from common PHY binding: should be "pcie". Example: