From patchwork Thu Apr 4 12:20:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 10885511 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF75D1669 for ; Thu, 4 Apr 2019 12:20:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DA53128A80 for ; Thu, 4 Apr 2019 12:20:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CD77728A85; Thu, 4 Apr 2019 12:20:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 740B928A80 for ; Thu, 4 Apr 2019 12:20:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729469AbfDDMUj (ORCPT ); Thu, 4 Apr 2019 08:20:39 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:3796 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727039AbfDDMUj (ORCPT ); Thu, 4 Apr 2019 08:20:39 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 04 Apr 2019 05:20:42 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 04 Apr 2019 05:20:38 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 04 Apr 2019 05:20:38 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 4 Apr 2019 12:20:38 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 4 Apr 2019 12:20:38 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 4 Apr 2019 12:20:38 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 04 Apr 2019 05:20:37 -0700 From: Vidya Sagar To: , , , , , CC: , , , , , Subject: [PATCH 1/2] PCI: dwc: Add API support to de-initialize host Date: Thu, 4 Apr 2019 17:50:23 +0530 Message-ID: <1554380425-29215-2-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554380425-29215-1-git-send-email-vidyas@nvidia.com> References: <1554380425-29215-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1554380442; bh=l3qukOoFZdlyyKPDCqt1jD+ayD6fA0VPt6yvZb0u4T4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=DzUsm6/p9vyZ3T80GWXLQT0b7bagS/VS/tE2r15nBi2IXqaF4AxR2zTpsNmFRuhts IDyaWSNEiRaOBEo/2y811ScQWCmCQxYq/cFWjAZVbJ+Sph5vuYh2RROs8AnWAfFLOm P8MU6khAFx0Vln7g7QhaH7STVwIKiT8NeVlhabVrnvAcEDdrygxLG69PGcGHpSjp/5 owOjmKfCQvvzmXt9++4WsVDEbt6G8o2Vd56O5vaSF7rCZeReKgm6EFahgdyQuxF2Qb qwHGw8zQRJN2BHH7a0XUYCwTeoqVxIhJIAEwpFmyf6cwRO2t/+bsFMV7SgIjKO9AjG 8v1MydK4p52gw== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add an API to group all the tasks to be done to de-initialize host which can then be called by any Designware core based driver implementations while adding .remove() support in their respective drivers. Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-designware-host.c | 7 +++++++ drivers/pci/controller/dwc/pcie-designware.h | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 3e4169e738a5..d7881490282d 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -516,6 +516,13 @@ int dw_pcie_host_init(struct pcie_port *pp) return ret; } +void dw_pcie_host_deinit(struct pcie_port *pp) +{ + pci_stop_root_bus(pp->root_bus); + pci_remove_root_bus(pp->root_bus); + dw_pcie_free_msi(pp); +} + static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val, bool write) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index adff0c713665..ea8d1caf11c5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -343,6 +343,7 @@ void dw_pcie_msi_init(struct pcie_port *pp); void dw_pcie_free_msi(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); +void dw_pcie_host_deinit(struct pcie_port *pp); int dw_pcie_allocate_domains(struct pcie_port *pp); #else static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) @@ -367,6 +368,10 @@ static inline int dw_pcie_host_init(struct pcie_port *pp) return 0; } +static inline void dw_pcie_host_deinit(struct pcie_port *pp) +{ +} + static inline int dw_pcie_allocate_domains(struct pcie_port *pp) { return 0;