From patchwork Fri Jul 15 11:59:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 12919141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BB03C43334 for ; Fri, 15 Jul 2022 12:28:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234699AbiGOM2Q (ORCPT ); Fri, 15 Jul 2022 08:28:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234052AbiGOM2E (ORCPT ); Fri, 15 Jul 2022 08:28:04 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE83D82FA3; Fri, 15 Jul 2022 05:28:02 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26F8p324004117; Fri, 15 Jul 2022 11:59:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id; s=qcppdkim1; bh=jReLj1U1PfgtLm6EGtYmbWuSw29A3TL63GS9rbvxQog=; b=QESqGkIg02S/xv+yiUSWyTr1p9rzFAe8J0Rs5eoxWKzPdXS6C2W/7A87seG2/qBpu2Dv aPEOLCVsG/gn+AHAxdkh0ts7Iypig3WQq4UDihFiY9EJZF/T8isLpT8ZnPVialZRY6UG oVUYQvWmNT43865czD1aDk4abnBwE5QQ8jkkwhvn9PichLiwZw6iWuYeiDo8L4b1ehAk 4iUuEC9WwAkte5tbs52OKtQgPzb3STV7hCN0EqV7PEDJsNIg9N/8XvNgQ+0Z6NSOTrd2 ODSRERKh+mdsWdMsUxVs69PyAivoXUmwZr273FpoTDfCR53OzZmdhVErknz6HkXddQGM cQ== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3hay68sdt5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Jul 2022 11:59:49 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 26FBxiqr007357; Fri, 15 Jul 2022 11:59:44 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3h72rjjfhx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 15 Jul 2022 11:59:44 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 26FBxiG7007352; Fri, 15 Jul 2022 11:59:44 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.37]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 26FBxi4Y007351; Fri, 15 Jul 2022 11:59:44 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 38B7A42E3; Fri, 15 Jul 2022 17:29:43 +0530 (+0530) From: Krishna chaitanya chundru To: helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, Krishna chaitanya chundru , Stanimir Varbanov , Andy Gross , Bjorn Andersson , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas Subject: [PATCH v3] PCI: qcom: Allow L1 and its sub states Date: Fri, 15 Jul 2022 17:29:25 +0530 Message-Id: <1657886366-32685-1-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: P4UbRrN_ykF2fK_iu9iffInOk0goZs4j X-Proofpoint-ORIG-GUID: P4UbRrN_ykF2fK_iu9iffInOk0goZs4j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-15_04,2022-07-15_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 mlxlogscore=891 spamscore=0 malwarescore=0 suspectscore=0 mlxscore=0 adultscore=0 impostorscore=0 priorityscore=1501 clxscore=1011 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2207150053 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Allow L1 and its sub-states in the qcom pcie driver. By default this is disabled in the qcom specific hardware. So enabling it explicitly only for controllers belonging to 2_7_0. This patch will not affect any link capability registers, this will allow the link transitions to L1 and its sub states only if they are already supported. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam ---- Changes since v1 & v2: - Update in the commit text only. Acked-by: Stanimir Varbanov --- drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a7202f0..5ef444f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -41,6 +41,9 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) +#define PCIE20_PARF_PM_CTRL 0x20 +#define REQ_NOT_ENTR_L1 BIT(5) + #define PCIE20_PARF_PHY_CTRL 0x40 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) @@ -1261,6 +1264,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) val |= BIT(4); writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + /* Enable L1 and L1ss */ + val = readl(pcie->parf + PCIE20_PARF_PM_CTRL); + val &= ~REQ_NOT_ENTR_L1; + writel(val, pcie->parf + PCIE20_PARF_PM_CTRL); + if (IS_ENABLED(CONFIG_PCI_MSI)) { val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); val |= BIT(31);