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Mon, 9 Jan 2023 12:57:09 -0600 Received: from xsjlizhih40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 9 Jan 2023 12:57:08 -0600 From: Lizhi Hou To: , , , , , CC: Lizhi Hou , , , , , , , Subject: [PATCH V6 3/3] PCI: Add PCI quirks to generate device tree node for Xilinx Alveo U50 Date: Mon, 9 Jan 2023 10:57:01 -0800 Message-ID: <1673290621-22888-4-git-send-email-lizhi.hou@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1673290621-22888-1-git-send-email-lizhi.hou@amd.com> References: <1673290621-22888-1-git-send-email-lizhi.hou@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C96C:EE_|SJ0PR12MB6903:EE_ X-MS-Office365-Filtering-Correlation-Id: b74b0686-2d38-4c8b-a006-08daf273500d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qsigRyYsR4wwSEeLmUkTaRufkF5KBUEJlpwMMnvTgWW1CW8CZOqQl/6ZWwd/X7VNBXTNc+BczXPGDjCGcGCHv9hhSnbyfGLEBXTI41JilC4YjWgAuWjY3RLy/34YQxDszMrNkpTCrd5k3mgmpHOYyUiTGZi0Xr7tLCecQ5in0UQf2peTi32fwdYdNtt5HEhdFAJCq6H4d4LgL/Ys4mIDgab4OyoeoYL+JiT0wzqUNEo4U8Y+dj7y3XLIUpYdEbSzQ4vQZ7EHGNoLpw9LUWgXn932lVzab3/LheP+dcVFmooAXF5z11yApxut3UekQIWKh/COw+43sYrcMwhpEdd28wuENzcrTBUPWsXOFl5O05q3ljHZ5fD97q/alfUksj2/Kok2bGWgCwm1AU3KV1dJpP2sYv7Mzh1tqiAh9+xxr8+oravO7FhqejAV/oA1K1v0aiWCovxSfJrlUxWAE6F4WFvZyRyn9y4ZJRl48MgUhWXxWopp505ewO7O1k7EYhmLK1yYN3FB7cgfIAKH1Ew6jwsj9mHkbptcAi+P2N+R0jRrIBsnmwjCvCgsgpO/GMo3oNGcisLKWHLJ9lCPLgOaKPrBjhmEo7K0DGvkivHwwgaIFK0u2rmmBeOuuZmuIhk96gPQzREHSVL8ww5te4UuX4F+GsRAuTSWpFTOWkrZBl6O0N98qKfgSGeg3W0qW8fgPVZnbiGp3h+e/pqdlqOvRLeUv4duc+jHckG/JQ9Ta3E= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(376002)(396003)(346002)(451199015)(36840700001)(40470700004)(46966006)(316002)(5660300002)(44832011)(40480700001)(26005)(186003)(478600001)(2616005)(40460700003)(426003)(47076005)(41300700001)(110136005)(54906003)(336012)(4326008)(70206006)(70586007)(8676002)(82310400005)(8936002)(86362001)(36756003)(6666004)(36860700001)(82740400003)(356005)(2906002)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2023 18:57:10.3639 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b74b0686-2d38-4c8b-a006-08daf273500d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C96C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6903 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Xilinx Alveo U50 PCI card exposes multiple hardware peripherals on its PCI BAR. The card firmware provides a flattened device tree to describe the hardware peripherals on its BARs. This allows U50 driver to load the flattened device tree and generate the device tree node for hardware peripherals underneath. To generate device tree node for U50 card, added PCI quirks to call of_pci_make_dev_node() for U50. Signed-off-by: Lizhi Hou Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Reviewed-by: Brian Xu --- drivers/pci/quirks.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 285acc4aaccc..f184cf51b800 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5992,3 +5992,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); #endif + +/* + * For PCI device which have multiple downstream devices, its driver may use + * a flattened device tree to describe the downstream devices. + * To overlay the flattened device tree, the PCI device and all its ancestor + * devices need to have device tree nodes on system base device tree. Thus, + * before driver probing, it might need to add a device tree node as the final + * fixup. + */ +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);