From patchwork Fri Jun 19 13:30:40 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Wilcox X-Patchwork-Id: 31355 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n5JDUgcp021262 for ; Fri, 19 Jun 2009 13:30:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752875AbZFSNai (ORCPT ); Fri, 19 Jun 2009 09:30:38 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1753128AbZFSNai (ORCPT ); Fri, 19 Jun 2009 09:30:38 -0400 Received: from palinux.external.hp.com ([192.25.206.14]:41538 "EHLO mail.parisc-linux.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752875AbZFSNah (ORCPT ); Fri, 19 Jun 2009 09:30:37 -0400 Received: by mail.parisc-linux.org (Postfix, from userid 26919) id 7587A494003; Fri, 19 Jun 2009 07:30:40 -0600 (MDT) Date: Fri, 19 Jun 2009 07:30:40 -0600 From: Matthew Wilcox To: linux-pci@vger.kernel.org Subject: [PATCH] Fix IRQ swizzling for ARI-enabled devices Message-ID: <20090619133039.GJ19977@parisc-linux.org> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org For many purposes, including interrupt-swizzling, devices with ARI enabled behave as if they have one device (number 0) and 256 functions. This probably hasn't bitten us in practice because all ARI devices I've seen are also IOV devices, and IOV devices are required to use MSI. This isn't guaranteed, and there are legitimate reasons to use ARI without IOV, and hence potentially use pin-based interrupts. Signed-off-by: Matthew Wilcox diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1a91bf9..407a5b9 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1511,11 +1511,18 @@ void pci_enable_ari(struct pci_dev *dev) * * Perform INTx swizzling for a device behind one level of bridge. This is * required by section 9.1 of the PCI-to-PCI bridge specification for devices - * behind bridges on add-in cards. + * behind bridges on add-in cards. For devices with ARI enabled, the slot + * number is always 0 (see the Implementation Note in section 2.2.8.1 of + * the PCI Express Base Specification, Revision 2.1) */ u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin) { - return (((pin - 1) + PCI_SLOT(dev->devfn)) % 4) + 1; + if (pci_ari_enabled(dev->bus)) + slot = 0; + else + slot = PCI_SLOT(dev->devfn)); + + return (((pin - 1) + slot) % 4) + 1; } int