diff mbox

pciutils: show SR-IOV VF BARs

Message ID 20090711005526.GH30379@sequoia.sous-sol.org (mailing list archive)
State Accepted, archived
Headers show

Commit Message

Chris Wright July 11, 2009, 12:55 a.m. UTC
When decoding the PCIe SR-IOV capability, cap_sriov() doesn't show the
VF BARs.  This patch shows basic information about the VF BARs (doesn't
include size, for example).  For example:
...
	Capabilities: [160] Single Root I/O Virtualization (SR-IOV)
		IOVCap: Migration-, Interrupt Message Number: 000
		IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+
		IOVSta: Migration-
		Initial VFs: 8, Total VFs: 8, Number of VFs: 8, Function Depende
ncy Link: 00
		VF offset: 128, stride: 2, Device ID: 10ca
		Supported Page Size: 00000553, System Page Size: 00000001
		Region 0: Memory at fbb20000 (64-bit, non-prefetchable)
		Region 3: Memory at fbb00000 (64-bit, non-prefetchable)
		VF Migration: offset: 00000000, BIR: 0
...
	Capabilities: [170] Single Root I/O Virtualization (SR-IOV)
		IOVCap: Migration-, Interrupt Message Number: 000
		IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+
		IOVSta: Migration-
		Initial VFs: 16, Total VFs: 16, Number of VFs: 16, Function Depe
ndency Link: 00
		VF offset: 1, stride: 1, Device ID: 5833
		Supported Page Size: 000007ff, System Page Size: 00000001
		Region 0: Memory at f0000000 (64-bit, prefetchable)
		Region 2: Memory at f8820000 (64-bit, prefetchable)
		Region 4: Memory at f8800000 (64-bit, prefetchable)
		VF Migration: offset: 00000000, BIR: 0

Signed-off-by: Chris Wright <chrisw@sous-sol.org>
---

 ls-ecaps.c |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

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Comments

Martin MareŇ° July 12, 2009, 8:50 p.m. UTC | #1
Hi!

> When decoding the PCIe SR-IOV capability, cap_sriov() doesn't show the
> VF BARs.  This patch shows basic information about the VF BARs (doesn't
> include size, for example).

Yes, this looks right.

Applied with some whitespace changes.

Also, I have improved dumping of addresses, so that it works with 32-bit
pciaddr_t, too.

You can check the result in the GIT repository.

				Have a nice fortnight
Chris Wright July 13, 2009, 5:11 p.m. UTC | #2
* Martin Mares (mj@ucw.cz) wrote:
> Applied with some whitespace changes.
> 
> Also, I have improved dumping of addresses, so that it works with 32-bit
> pciaddr_t, too.
> 
> You can check the result in the GIT repository.

Looks good, thanks for the additional cleanups.
-chris
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diff mbox

Patch

diff --git a/ls-ecaps.c b/ls-ecaps.c
index 38da824..ff8514f 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -145,6 +145,7 @@  cap_sriov(struct device *d, int where)
   u16 b;
   u16 w;
   u32 l;
+  int i;
 
   printf("Single Root I/O Virtualization (SR-IOV)\n");
   if (verbose < 2)
@@ -181,6 +182,28 @@  cap_sriov(struct device *d, int where)
   printf("\t\tSupported Page Size: %08x, ", l);
   l = get_conf_long(d, where + PCI_IOV_SYSPS);
   printf("System Page Size: %08x\n", l);
+  for (i=0; i<PCI_IOV_NUM_BAR; i++) {
+    pciaddr_t addr;
+    int type;
+    u32 h;
+    l = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
+    if (l == 0xffffffff)
+      l = 0;
+    if (!l)
+      continue;
+    printf("\t\tRegion %d: Memory at ", i);
+    addr = l & PCI_ADDR_MEM_MASK;
+    type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
+    if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
+       i++;
+       h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
+       addr |= (pciaddr_t)h<<32;
+    }  
+    printf(PCIADDR_T_FMT, addr);
+    printf(" (%s-bit, %sprefetchable)\n",
+           (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
+           (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
+  }
   l = get_conf_long(d, where + PCI_IOV_MSAO);
   printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
 	PCI_IOV_MSA_BIR(l));