From patchwork Fri Aug 28 18:14:54 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 44535 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n7SIDwRN009186 for ; Fri, 28 Aug 2009 18:14:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751894AbZH1SOs (ORCPT ); Fri, 28 Aug 2009 14:14:48 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751911AbZH1SOs (ORCPT ); Fri, 28 Aug 2009 14:14:48 -0400 Received: from g5t0008.atlanta.hp.com ([15.192.0.45]:19931 "EHLO g5t0008.atlanta.hp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751894AbZH1SOs (ORCPT ); Fri, 28 Aug 2009 14:14:48 -0400 Received: from g1t0039.austin.hp.com (g1t0039.austin.hp.com [16.236.32.45]) by g5t0008.atlanta.hp.com (Postfix) with ESMTP id 736DB2432F; Fri, 28 Aug 2009 18:14:50 +0000 (UTC) Received: from ldl (linux.corp.hp.com [15.11.146.101]) by g1t0039.austin.hp.com (Postfix) with ESMTP id 430DD3409B; Fri, 28 Aug 2009 18:14:50 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by ldl (Postfix) with ESMTP id 1C6C91A7E0A5; Fri, 28 Aug 2009 12:14:50 -0600 (MDT) Received: from ldl ([127.0.0.1]) by localhost (localhost [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id h1DRbYno+c0F; Fri, 28 Aug 2009 12:14:50 -0600 (MDT) Received: from eh.fc.hp.com (eh.fc.hp.com [15.11.146.105]) by ldl (Postfix) with ESMTP id 040EA1A7E0A3; Fri, 28 Aug 2009 12:14:50 -0600 (MDT) Received: from bob.kio (localhost [127.0.0.1]) by eh.fc.hp.com (Postfix) with ESMTP id 15A7A26169; Fri, 28 Aug 2009 12:14:54 -0600 (MDT) Subject: [PATCH 2 4/9] PCI hotplug: add pci_configure_slot() To: Kristen Carlson Accardi From: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, Rolf Eike Beer , Gary Hade , Kenji Kaneshige Date: Fri, 28 Aug 2009 12:14:54 -0600 Message-ID: <20090828181454.29033.57178.stgit@bob.kio> In-Reply-To: <20090828181352.29033.93053.stgit@bob.kio> References: <20090828181352.29033.93053.stgit@bob.kio> User-Agent: StGit/0.14.3.386.gb02d MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch adds a new pci_configure_slot() function that programs the PCI bus characteristics for a newly-added device. This is based on code from pciehp_pci.c, but should be generic enough to be used by pciehp, shpchp, and acpiphp. We could move pci_configure_slot() somewhere more generic if similar functionality is ever implemented for non-ACPI systems. Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Chiang --- drivers/pci/hotplug/acpi_pcihp.c | 167 ++++++++++++++++++++++++++++++++++++++ drivers/pci/hotplug/pcihp_slot.c | 0 include/linux/pci_hotplug.h | 3 + 3 files changed, 168 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/hotplug/pcihp_slot.c -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/hotplug/acpi_pcihp.c b/drivers/pci/hotplug/acpi_pcihp.c index 5a448ad..cb8bbd8 100644 --- a/drivers/pci/hotplug/acpi_pcihp.c +++ b/drivers/pci/hotplug/acpi_pcihp.c @@ -1,7 +1,11 @@ /* * Common ACPI functions for hot plug platforms * - * Copyright (C) 2006 Intel Corporation + * Copyright (C) 2003-2004, 2006 Intel Corporation + * Copyright (C) 1995,2001 Compaq Computer Corporation + * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) + * Copyright (C) 2001 IBM Corp. + * (c) Copyright 2009 Hewlett-Packard Development Company, L.P. * * All rights reserved. * @@ -21,7 +25,6 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * Send feedback to - * */ #include @@ -364,6 +367,166 @@ int acpi_get_hp_params(struct pci_dev *dev, struct hotplug_params *hpp) } EXPORT_SYMBOL_GPL(acpi_get_hp_params); +static struct hpp_type0 pci_default_type0 = { + .revision = 1, + .cache_line_size = 8, + .latency_timer = 0x40, + .enable_serr = 0, + .enable_perr = 0, +}; + +static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp) +{ + u16 pci_cmd, pci_bctl; + + if (hpp->revision > 1) { + dev_warn(&dev->dev, + "PCI setting record rev %d not supported\n", + hpp->revision); + return; + } + + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer); + pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); + if (hpp->enable_serr) + pci_cmd |= PCI_COMMAND_SERR; + else + pci_cmd &= ~PCI_COMMAND_SERR; + if (hpp->enable_perr) + pci_cmd |= PCI_COMMAND_PARITY; + else + pci_cmd &= ~PCI_COMMAND_PARITY; + pci_write_config_word(dev, PCI_COMMAND, pci_cmd); + + /* Program bridge control value */ + if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { + pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, + hpp->latency_timer); + pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); + if (hpp->enable_serr) + pci_bctl |= PCI_BRIDGE_CTL_SERR; + else + pci_bctl &= ~PCI_BRIDGE_CTL_SERR; + if (hpp->enable_perr) + pci_bctl |= PCI_BRIDGE_CTL_PARITY; + else + pci_bctl &= ~PCI_BRIDGE_CTL_PARITY; + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); + } +} + +static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) +{ + int pos; + u16 reg16; + u32 reg32; + + /* Find PCI Express capability */ + pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + if (!pos) + return; + + if (hpp->revision > 1) { + dev_warn(&dev->dev, + "PCI Express setting record rev %d not supported\n", + hpp->revision); + return; + } + + /* Initialize Device Control Register */ + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16); + reg16 = (reg16 & hpp->pci_exp_devctl_and) | hpp->pci_exp_devctl_or; + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16); + + /* Initialize Link Control Register */ + if (dev->subordinate) { + pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, ®16); + reg16 = (reg16 & hpp->pci_exp_lnkctl_and) + | hpp->pci_exp_lnkctl_or; + pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, reg16); + } + + /* Find Advanced Error Reporting Enhanced Capability */ + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); + if (!pos) + return; + + /* Initialize Uncorrectable Error Mask Register */ + pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); + reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or; + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); + + /* Initialize Uncorrectable Error Severity Register */ + pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); + reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or; + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); + + /* Initialize Correctable Error Mask Register */ + pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); + reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or; + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); + + /* Initialize Advanced Error Capabilities and Control Register */ + pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); + reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or; + pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); + + /* + * FIXME: The following two registers are not supported yet. + * + * o Secondary Uncorrectable Error Severity Register + * o Secondary Uncorrectable Error Mask Register + */ +} + +void pci_configure_slot(struct pci_dev *dev) +{ + struct pci_dev *cdev; + struct hotplug_params hpp; + struct hpp_type0 *type0 = NULL; + int ret; + + if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL || + (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && + (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI))) + return; + + memset(&hpp, 0, sizeof(hpp)); + ret = acpi_get_hp_params(dev, &hpp); + if (ret == 0 && hpp.t0) + type0 = hpp.t0; + else { + /* + * Maybe we *should* use default PCI settings for PCIe devices; + * this merely preserves the behavior of pciehp, which didn't + * supply any default Type 0 settings. + */ + if (!dev->is_pcie) { + type0 = &pci_default_type0; + dev_warn(&dev->dev, + "no PCI setting record; using defaults\n"); + } + } + + if (hpp.t2) + program_hpp_type2(dev, hpp.t2); + + if (hpp.t1) + dev_info(&dev->dev, + "PCI-X setting record not supported\n"); + + if (type0) + program_hpp_type0(dev, type0); + + if (dev->subordinate) { + list_for_each_entry(cdev, &dev->subordinate->devices, + bus_list) + pci_configure_slot(cdev); + } +} +EXPORT_SYMBOL_GPL(pci_configure_slot); + /** * acpi_get_hp_hw_control_from_firmware * @dev: the pci_dev of the bridge that has a hotplug controller diff --git a/drivers/pci/hotplug/pcihp_slot.c b/drivers/pci/hotplug/pcihp_slot.c new file mode 100644 index 0000000..e69de29 diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h index 0f3e1db..ab8a05b 100644 --- a/include/linux/pci_hotplug.h +++ b/include/linux/pci_hotplug.h @@ -230,6 +230,9 @@ int acpi_get_hp_params(struct pci_dev *dev, struct hotplug_params *hpp); int acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev, u32 flags); int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle); int acpi_pci_detect_ejectable(struct pci_bus *pbus); +void pci_configure_slot(struct pci_dev *dev); +#else +static inline void pci_configure_slot(struct pci_dev *dev) { } #endif #endif