From patchwork Wed Mar 10 03:26:48 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dean Nelson X-Patchwork-Id: 84449 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2A3QpKC015748 for ; Wed, 10 Mar 2010 03:26:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756223Ab0CJD0u (ORCPT ); Tue, 9 Mar 2010 22:26:50 -0500 Received: from mx1.redhat.com ([209.132.183.28]:57433 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756221Ab0CJD0u (ORCPT ); Tue, 9 Mar 2010 22:26:50 -0500 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id o2A3Qnrs016540 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 9 Mar 2010 22:26:49 -0500 Received: from [127.0.0.1] (vpn-250-65.phx2.redhat.com [10.3.250.65]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id o2A3Qm4d006866; Tue, 9 Mar 2010 22:26:49 -0500 Date: Tue, 9 Mar 2010 22:26:48 -0500 From: Dean Nelson To: jbarnes@virtuousgeek.org Cc: netdev@vger.kernel.org, linux-pci@vger.kernel.org Message-Id: <20100310032647.6331.70590.send-patch@aqua> In-Reply-To: <20100310032632.6331.15414.send-patch@aqua> References: <20100310032632.6331.15414.send-patch@aqua> Subject: [PATCH 2/3] pci: fix access of PCI_X_CMD by pcix get and set mmrbc functions X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 10 Mar 2010 03:26:51 +0000 (UTC) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1decd4f..cdf201e 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2585,13 +2585,13 @@ EXPORT_SYMBOL(pcix_get_max_mmrbc); int pcix_get_mmrbc(struct pci_dev *dev) { int ret, cap; - u32 cmd; + u16 cmd; cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); if (!cap) return -EINVAL; - ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); + ret = pci_read_config_word(dev, cap + PCI_X_CMD, &cmd); if (!ret) ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); @@ -2611,7 +2611,8 @@ EXPORT_SYMBOL(pcix_get_mmrbc); int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) { int cap, err = -EINVAL; - u32 stat, cmd, v, o; + u32 stat, v, o; + u16 cmd; if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) goto out; @@ -2629,7 +2630,7 @@ int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) return -E2BIG; - err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); + err = pci_read_config_word(dev, cap + PCI_X_CMD, &cmd); if (err) goto out; @@ -2641,7 +2642,7 @@ int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) cmd &= ~PCI_X_CMD_MAX_READ; cmd |= v << 2; - err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); + err = pci_write_config_word(dev, cap + PCI_X_CMD, cmd); } out: return err;