From patchwork Thu Mar 25 20:03:30 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Duyck, Alexander H" X-Patchwork-Id: 88314 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o2PK3arE019810 for ; Thu, 25 Mar 2010 20:03:36 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752160Ab0CYUDf (ORCPT ); Thu, 25 Mar 2010 16:03:35 -0400 Received: from mga09.intel.com ([134.134.136.24]:35668 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751180Ab0CYUDf (ORCPT ); Thu, 25 Mar 2010 16:03:35 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 25 Mar 2010 13:00:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.51,309,1267430400"; d="scan'208";a="503669481" Received: from gitlad.jf.intel.com ([10.23.21.59]) by orsmga002.jf.intel.com with ESMTP; 25 Mar 2010 13:02:39 -0700 Received: from gitlad.jf.intel.com (gitlad.jf.intel.com [127.0.0.1]) by gitlad.jf.intel.com (8.14.2/8.14.2) with ESMTP id o2PK3U0a016855 for ; Thu, 25 Mar 2010 13:03:30 -0700 From: Alexander Duyck Subject: [PATCH] aerdrv: use correct bit defines and add 2ms delay to aer_root_reset To: linux-pci@vger.kernel.org Date: Thu, 25 Mar 2010 13:03:30 -0700 Message-ID: <20100325200330.16823.6038.stgit@gitlad.jf.intel.com> User-Agent: StGIT/0.14.2 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 25 Mar 2010 20:03:36 +0000 (UTC) diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c index 21f215f..6b7726d 100644 --- a/drivers/pci/pcie/aer/aerdrv.c +++ b/drivers/pci/pcie/aer/aerdrv.c @@ -243,11 +243,17 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) /* Assert Secondary Bus Reset */ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl); - p2p_ctrl |= PCI_CB_BRIDGE_CTL_CB_RESET; + p2p_ctrl |= PCI_BRIDGE_CTL_BUS_RESET; pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl); + /* + * we should send hot reset message for 2ms to allow it time to + * propogate to all downstream ports + */ + msleep(2); + /* De-assert Secondary Bus Reset */ - p2p_ctrl &= ~PCI_CB_BRIDGE_CTL_CB_RESET; + p2p_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl); /*