From patchwork Mon Jul 9 20:32:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1174701 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id C1E6E40B21 for ; Mon, 9 Jul 2012 20:32:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753279Ab2GIUcJ (ORCPT ); Mon, 9 Jul 2012 16:32:09 -0400 Received: from mail-fa0-f74.google.com ([209.85.161.74]:46745 "EHLO mail-fa0-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752976Ab2GIUcG (ORCPT ); Mon, 9 Jul 2012 16:32:06 -0400 Received: by fat25 with SMTP id 25so573213fat.1 for ; Mon, 09 Jul 2012 13:32:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=qwazmEFlfiox5+LhxDC1GF2KdeCCOc2swMAkesQYQ2w=; b=N1ZInQ4o9RXR7rOJVdw06PC/GsBRaDv33fEUZLqtGGMK9uKc6+cR/Z32oZ80n0sipN s5nBqE7FOuIcOgbXrbcFqEwIyhDsTvZYdIre6l6wxPHseqWRW7SVhSwvGsKLBQvSEu6B JEabfaHH6TTPbLlumq9ePCD2GEgyFcbo/qV/3/yUqTvyE6IeVL7oTpH1iru8VBt0jM09 uL2SLAxQ8FFQRsS+Y3LzF76zMzFnqUsZde+u/gpQ3iSSd8SDwBGGWtX0BLJBZ32m265b ES1tvxQGGyu5Ge+81w2JxNE6TH1E5dJwKbJapAr/jRXvqrutigL9RGz4dJ6jqYPjDWri 6fVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=qwazmEFlfiox5+LhxDC1GF2KdeCCOc2swMAkesQYQ2w=; b=LhlsYpY5HqsA5WXxw8qOMNUqp4komWbnNJI8/8yyROx9nVgckbOZskv3D7keQ107x8 tbZOYPtkLgV4S96pW4AxbUxP4lgwKz3ffSrKFfNoA0hmKOjUchwvW6VpKPqrl6uOpA+y 9JQHVhVxOLBYN+sBoBxCiGJlbxuQwmAIN19J0mNzbioNqizwiLPUBZS4jVPNObkJHCGO s2Ic2OwD729adVpDLr2DShUS8/+ZWhmCGaZadAHbwK7Vzc/YQub4F0BOMbmTkR/as0dM 5hGMkeXPx4AwYC15C+EW/e2THp3UTnTfULlPGiiGvCx62ItbI9CTu98A8mbsfOCvnra5 X4eA== Received: by 10.14.28.65 with SMTP id f41mr13268724eea.11.1341865924813; Mon, 09 Jul 2012 13:32:04 -0700 (PDT) Received: by 10.14.28.65 with SMTP id f41mr13268714eea.11.1341865924687; Mon, 09 Jul 2012 13:32:04 -0700 (PDT) Received: from hpza9.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id v14si23178079eef.2.2012.07.09.13.32.04 (version=TLSv1/SSLv3 cipher=AES128-SHA); Mon, 09 Jul 2012 13:32:04 -0700 (PDT) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.18.96.155]) by hpza9.eem.corp.google.com (Postfix) with ESMTP id 7C8075C0050; Mon, 9 Jul 2012 13:32:04 -0700 (PDT) Received: from bhelgaas.mtv.corp.google.com (unknown [IPv6:::1]) by bhelgaas.mtv.corp.google.com (Postfix) with ESMTP id E1AF91806EA; Mon, 9 Jul 2012 13:32:03 -0700 (PDT) Subject: [PATCH 1/3] PCI: allow P2P bridge windows starting at PCI bus address zero To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: Daniel Yeisley , Yinghai Lu , linux-kernel@vger.kernel.org, "David S. Miller" Date: Mon, 09 Jul 2012 14:32:03 -0600 Message-ID: <20120709203203.28178.15800.stgit@bhelgaas.mtv.corp.google.com> In-Reply-To: <20120709202308.28178.58942.stgit@bhelgaas.mtv.corp.google.com> References: <20120709202308.28178.58942.stgit@bhelgaas.mtv.corp.google.com> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmBMbkIE8TuPy929v5eXc1FK8U7cRtQODLmfb+17p6p+6nq+b+zL1+IQ5FBmTmSrYmInrOYBsbKQLjgd4v7thlh85Syze1KnPozw5Fd2Yh4KIazb9kFF/B4KiOLbWWvyb3wfF2F+Y5DRKNQLyB5U6fRkXHgsaykFhdDWbXDOBWwchWWZxdBfSmPhaK7GHvlKAWpsFtz Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org cd81e1ea1a4c added checks that prevent us from using P2P bridge windows that start at PCI bus address zero. The reason was to "prevent us from overwriting resources that are unassigned." But generic code should allow address zero in both BARs and bridge windows, so I think that commit was a mistake. Windows at bus address zero are legal and likely to exist on machines with an offset between bus addresses and CPU addresses. For example, in the following hypothetical scenario, the bridge at 00:01.0 has a window at bus address zero and the device at 01:00.0 has a BAR at bus address zero, and I think both are perfectly valid: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x100000000-0x1ffffffff] (bus address [0x00000000-0xffffffff]) pci 0000:00:01.0: PCI bridge to [bus 01] pci 0000:00:01.0: bridge window [mem 0x100000000-0x100ffffff] pci 0000:01:00.0: reg 10: [mem 0x100000000-0x100ffffff] CC: Yinghai Lu Signed-off-by: Bjorn Helgaas Acked-by: Yinghai Lu --- drivers/pci/probe.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 658ac97..9c5d2a9 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -287,7 +287,7 @@ static void __devinit pci_read_bridge_io(struct pci_bus *child) limit |= (io_limit_hi << 16); } - if (base && base <= limit) { + if (base <= limit) { res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; res2.flags = res->flags; region.start = base; @@ -314,7 +314,7 @@ static void __devinit pci_read_bridge_mmio(struct pci_bus *child) pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; - if (base && base <= limit) { + if (base <= limit) { res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; region.start = base; region.end = limit + 0xfffff; @@ -360,7 +360,7 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) #endif } } - if (base && base <= limit) { + if (base <= limit) { res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; if (res->flags & PCI_PREF_RANGE_TYPE_64)