From patchwork Fri May 24 16:59:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryce Lelbach X-Patchwork-Id: 2612131 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id BAF0F40079 for ; Fri, 24 May 2013 17:33:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757215Ab3EXRdp (ORCPT ); Fri, 24 May 2013 13:33:45 -0400 Received: from newmail.cct.lsu.edu ([130.39.21.13]:53735 "EHLO envelope.cct.lsu.edu" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1757154Ab3EXRdo (ORCPT ); Fri, 24 May 2013 13:33:44 -0400 Received: from localhost (hermione.cct.lsu.edu [130.39.12.224]) (using TLSv1 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by envelope.cct.lsu.edu (Postfix) with ESMTP id 9188D205844C for ; Fri, 24 May 2013 11:59:49 -0500 (CDT) Date: Fri, 24 May 2013 11:59:49 -0500 From: Bryce Lelbach To: linux-pci@vger.kernel.org Subject: Patch: Increase maximum bus memory window size (for Xeon Phi) Message-ID: <20130524165947.GA2487@pyxis.br.cox.net> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The attached patch affects pbus_size_mem() in drivers/pci/setup-bus.c. The patch increases the maximum memory window size for a PCI bus from 2 Gb to 2^63 Gb. This change is necessary to support Intel Xeon Phi co-processors. These co-processors are PCIe devices used for high-performance computing applications. The device requires an 8Gb memory window to function (the co-processor has 8Gb of onboard memory). This patch is a modified version of a patch from Intel's MPSS framework (specifically, from the "KNC_gold_update_1-2.1.4982-15-rhel-6.3" package), which will apply to a 3.7.8 kernel (I am about to try it on a 3.8 kernel). To the best of my knowledge, newer RHEL kernels are shipped with this patch. diff -u -r -N linux-source-3.7/drivers/pci/setup-bus.c linux-source-3.7-xeon-phi/drivers/pci/setup-bus.c --- linux-source-3.7/drivers/pci/setup-bus.c 2013-02-14 12:57:59.000000000 -0600 +++ linux-source-3.7-xeon-phi/drivers/pci/setup-bus.c 2013-02-20 18:08:16.000000000 -0600 @@ -852,7 +852,7 @@ { struct pci_dev *dev; resource_size_t min_align, align, size, size0, size1; - resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ + resource_size_t aligns[44]; /* Alignments from 1Mb to 2^63 */ int order, max_order; struct resource *b_res = find_free_bus_resource(bus, type); unsigned int mem64_mask = 0; @@ -891,7 +891,8 @@ /* For bridges size != alignment */ align = pci_resource_alignment(dev, r); order = __ffs(align) - 20; - if (order > 11) { + if ((sizeof(size_t) == 4 && order > 11) || + (sizeof(size_t) == 8 && order > 43)) { dev_warn(&dev->dev, "disabling BAR %d: %pR " "(bad alignment %#llx)\n", i, r, (unsigned long long) align);