From patchwork Tue Aug 6 20:19:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Borislav Petkov X-Patchwork-Id: 2839591 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CFD96BF535 for ; Tue, 6 Aug 2013 20:19:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D326D201B5 for ; Tue, 6 Aug 2013 20:19:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C16B7200E1 for ; Tue, 6 Aug 2013 20:19:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756332Ab3HFUT3 (ORCPT ); Tue, 6 Aug 2013 16:19:29 -0400 Received: from mail.skyhub.de ([78.46.96.112]:39005 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756235Ab3HFUT2 (ORCPT ); Tue, 6 Aug 2013 16:19:28 -0400 X-Virus-Scanned: Nedap ESD1 at mail.skyhub.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alien8.de; s=alien8; t=1375820367; bh=m9phu4IpFeZCUPVC4lfNyRzQVNKu6z8tb1fILcCOupM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:In-Reply-To; b=CUYHLSMgkC4GyjjHjOOFxxMSwsGAlDmmrC1KuJ HdgZNttVf5IRry5YeaGnoXNODfFIDFVxvKri9H3E3LeUUWFytDIiNExBjff6cY5df6/ JvkUQwR8nJxyiJOmcwrW3vJjAu+Fk8+R3GljW5jrltWstxOjQHn4y4EspvKPoOUg/0= Received: from mail.skyhub.de ([127.0.0.1]) by localhost (door.skyhub.de [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 9J4WTNMFQcSM; Tue, 6 Aug 2013 22:19:27 +0200 (CEST) Received: from liondog.tnic (p54B7EA17.dip0.t-ipconnect.de [84.183.234.23]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 886581D95E8; Tue, 6 Aug 2013 22:19:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alien8.de; s=alien8; t=1375820367; bh=m9phu4IpFeZCUPVC4lfNyRzQVNKu6z8tb1fILcCOupM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:In-Reply-To; b=CUYHLSMgkC4GyjjHjOOFxxMSwsGAlDmmrC1KuJ HdgZNttVf5IRry5YeaGnoXNODfFIDFVxvKri9H3E3LeUUWFytDIiNExBjff6cY5df6/ JvkUQwR8nJxyiJOmcwrW3vJjAu+Fk8+R3GljW5jrltWstxOjQHn4y4EspvKPoOUg/0= Received: by liondog.tnic (Postfix, from userid 1000) id F08FB1015A6; Tue, 6 Aug 2013 22:19:25 +0200 (CEST) Date: Tue, 6 Aug 2013 22:19:25 +0200 From: Borislav Petkov To: Aravind Gopalakrishnan Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, dougthompson@xmission.com, bhelgaas@google.com, jbeulich@suse.com, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH 2/3 V2] EDAC, AMD64_EDAC: Add relevant condition checks as F15h M30h does not support GART or L3. Message-ID: <20130806201925.GG14891@pd.tnic> References: <1375483384-2302-1-git-send-email-Aravind.Gopalakrishnan@amd.com> <1375483384-2302-3-git-send-email-Aravind.Gopalakrishnan@amd.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1375483384-2302-3-git-send-email-Aravind.Gopalakrishnan@amd.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Fri, Aug 02, 2013 at 05:43:03PM -0500, Aravind Gopalakrishnan wrote: > Adding code to check for specific model (F15h, M30h) and if yes, > do not add flag AMD_NB_GART. Also check cpuid_edx(0x80000006) for > prescence of L3. If no L3, do not add any L3 flags. > > Signed-off-by: Aravind Gopalakrishnan > > diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c > index 3048ded..3ee7a4d 100644 > --- a/arch/x86/kernel/amd_nb.c > +++ b/arch/x86/kernel/amd_nb.c > @@ -20,6 +20,7 @@ const struct pci_device_id amd_nb_misc_ids[] = { > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, > + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, > {} > }; > @@ -27,6 +28,7 @@ EXPORT_SYMBOL(amd_nb_misc_ids); > > static const struct pci_device_id amd_nb_link_ids[] = { > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }, > + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) }, > { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) }, > {} > }; > @@ -81,13 +83,21 @@ int amd_cache_northbridges(void) > next_northbridge(misc, amd_nb_misc_ids); > node_to_amd_nb(i)->link = link = > next_northbridge(link, amd_nb_link_ids); > - } > + } > > + /* GART present only on Fam15h upto model 0fh */ > if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || > - boot_cpu_data.x86 == 0x15) > + (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) > amd_northbridges.flags |= AMD_NB_GART; > > /* > + * Check CPUID Fn8000_0006_EDX: L3 Cache Identifiers. > + * If == 0, then no need to proceed as there is no L3. This comment explains the code. Just sit down and think about it: does it make any sense to have that in a comment? > + */ > + if (cpuid_edx(0x80000006) == 0) > + return 0; > + > + /* > * Some CPU families support L3 Cache Index Disable. There are some > * limitations because of E382 and E388 on family 0x10. > */ > -- I fixed it up like this: commit a0cb1bab68823648def0fda19bf307ad08eb25d2 Author: Aravind Gopalakrishnan Date: Fri Aug 2 17:43:03 2013 -0500 x86, amd_nb: Clarify F15h, model 30h GART and L3 support F15h, models 0x30 and later don't have a GART. Note that. Also check cpuid_edx(0x80000006) for prescence of L3 because there are models which don't sport an L3. Signed-off-by: Aravind Gopalakrishnan [ Boris: rewrite commit message, cleanup comments. ] Signed-off-by: Borislav Petkov diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 3048ded1b598..59554dca96ec 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -20,6 +20,7 @@ const struct pci_device_id amd_nb_misc_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, {} }; @@ -27,6 +28,7 @@ EXPORT_SYMBOL(amd_nb_misc_ids); static const struct pci_device_id amd_nb_link_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) }, {} }; @@ -81,13 +83,20 @@ int amd_cache_northbridges(void) next_northbridge(misc, amd_nb_misc_ids); node_to_amd_nb(i)->link = link = next_northbridge(link, amd_nb_link_ids); - } + } + /* GART present only on Fam15h upto model 0fh */ if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || - boot_cpu_data.x86 == 0x15) + (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) amd_northbridges.flags |= AMD_NB_GART; /* + * Check for L3 cache presence. + */ + if (!cpuid_edx(0x80000006)) + return 0; + + /* * Some CPU families support L3 Cache Index Disable. There are some * limitations because of E382 and E388 on family 0x10. */