From patchwork Fri Dec 6 00:19:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 3291761 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 15521C0D4A for ; Fri, 6 Dec 2013 00:20:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2A932204FB for ; Fri, 6 Dec 2013 00:19:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 41EFF204EB for ; Fri, 6 Dec 2013 00:19:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752702Ab3LFAT5 (ORCPT ); Thu, 5 Dec 2013 19:19:57 -0500 Received: from mail-ob0-f170.google.com ([209.85.214.170]:57204 "EHLO mail-ob0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752956Ab3LFAT5 (ORCPT ); Thu, 5 Dec 2013 19:19:57 -0500 Received: by mail-ob0-f170.google.com with SMTP id wp18so18704191obc.15 for ; Thu, 05 Dec 2013 16:19:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=IuRaO4/eg1BYWYVQ6ElqCIW1ojIsW1AKonSLhs9AvBk=; b=OkOffr6AMNOEBwbkqSWPPH7kiabU1Dvyp3auynWDpGWIrwsqWYGBetbAqsm5cWg74T mviGvEw3fre05Okw4JA0Y/eEy3RR+WyMLJEjBs66XYYOAY9/uRuJTabI/PBA8bBycS5e wqCzWb7A14Jfujn047AkV265ehweJPBB9vib0EWOBDdXuFiGiVat9zKnhb2MBlGU/P2K +57nQrY8un6HLxZ/AxHOFhSRbYxRKTNKQ4Zlp3W7YLt91+H6PeLjhF9FPLpGbFmlJjgU ZSLLAQKPXAZeRDjsx68G1qm0+Oig8T6Ud73H0wT+Wa7IMymZ19rAGWE0posPjASzIh3L c5tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:subject:to:from:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-type :content-transfer-encoding; bh=IuRaO4/eg1BYWYVQ6ElqCIW1ojIsW1AKonSLhs9AvBk=; b=E4U7yZNM+5ORpPiRFyBm5MFJqvDZEjyGhUXJK6lky7LgzyKDisQ8zzOedM3NltNbc4 SRDx2gnEd0fNtp7ZDd+c/nU6gyym89ZECGP5dU0cbR4CuVjNCPyt1Mu08jnbJHxDKG9p PaNrH5JcnWsCo44HcsyjnI8qygTBQDj1vjMe6ikCAFNHPQoDd04pzvGqGq86uZrcr3Ml BZ02IKe3Egp0cWVSJT5Fe96uiku3vMr7TPVe4CrDkkDSUs0mSHRMEgmwUo0EdF5SrlAo /VE0griRfZcB0JubIc75mVw2F7sjxNPQWBWn081bwKqVkFYvNMjpVWgHChYjUwjm/Zen WH8A== X-Gm-Message-State: ALoCoQmwaUZKnDrmEiC+DdwBlkdc5VceEJbUU1YVeP2Om7uEO0BTzc2wWUk656Kx2W4cR/sdnU0CyxlWUDDjdje7UxK/tNTtDEKqL7tn/8oePC0CBE2SZHzw0JRqGkzF0J/jvbXUNMV5hbY/Y9bFjY4MI8cLetAvvugZYfSjQnnFoKNU0YPG9zeHD7Ap+BKgBUN2Ziv/QHcA0jMOgZy/IMtmbg0RE/m+bxE+cSz3gKQPysJiEeqk9z0= X-Received: by 10.60.138.136 with SMTP id qq8mr366997oeb.59.1386289196692; Thu, 05 Dec 2013 16:19:56 -0800 (PST) Received: from localhost ([216.160.131.133]) by mx.google.com with ESMTPSA id dh4sm15903226obb.3.2013.12.05.16.19.55 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 05 Dec 2013 16:19:56 -0800 (PST) Subject: [PATCH 2/2] PCI: Stop clearing bridge Secondary Status when setting up I/O aperture To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: Jason Gunthorpe Date: Thu, 05 Dec 2013 17:19:55 -0700 Message-ID: <20131206001954.27659.78163.stgit@bhelgaas-glaptop.roam.corp.google.com> In-Reply-To: <20131206001333.27659.59935.stgit@bhelgaas-glaptop.roam.corp.google.com> References: <20131206001333.27659.59935.stgit@bhelgaas-glaptop.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP pci_setup_bridge_io() accessed PCI_IO_BASE and PCI_IO_LIMIT using dword (32-bit) reads and writes, which also access the Secondary Status register. Since the Secondary Status register is in the upper 16 bits of the dword, and we preserved those upper 16 bits, this had the effect of clearing any of the write-1-to-clear bits that happened to be set in the Secondary Status register. That's not what we want, so use word (16-bit) accesses to update only PCI_IO_BASE and PCI_IO_LIMIT. Signed-off-by: Bjorn Helgaas --- drivers/pci/setup-bus.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 80350299a6ea..2e344a5581ae 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -538,7 +538,8 @@ static void pci_setup_bridge_io(struct pci_bus *bus) struct pci_bus_region region; unsigned long io_mask; u8 io_base_lo, io_limit_lo; - u32 l, io_upper16; + u16 l; + u32 io_upper16; io_mask = PCI_IO_RANGE_MASK; if (bridge->io_window_1k) @@ -548,11 +549,10 @@ static void pci_setup_bridge_io(struct pci_bus *bus) res = bus->resource[0]; pcibios_resource_to_bus(bridge, ®ion, res); if (res->flags & IORESOURCE_IO) { - pci_read_config_dword(bridge, PCI_IO_BASE, &l); - l &= 0xffff0000; + pci_read_config_word(bridge, PCI_IO_BASE, &l); io_base_lo = (region.start >> 8) & io_mask; io_limit_lo = (region.end >> 8) & io_mask; - l |= ((u32) io_limit_lo << 8) | io_base_lo; + l = ((u16) io_limit_lo << 8) | io_base_lo; /* Set up upper 16 bits of I/O base/limit. */ io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); dev_info(&bridge->dev, " bridge window %pR\n", res); @@ -564,7 +564,7 @@ static void pci_setup_bridge_io(struct pci_bus *bus) /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); /* Update lower 16 bits of I/O base/limit. */ - pci_write_config_dword(bridge, PCI_IO_BASE, l); + pci_write_config_word(bridge, PCI_IO_BASE, l); /* Update upper 16 bits of I/O base/limit. */ pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); }