From patchwork Mon Dec 9 07:12:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush ANAND X-Patchwork-Id: 3309011 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3C710C0D4A for ; Mon, 9 Dec 2013 07:13:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 55A4720220 for ; Mon, 9 Dec 2013 07:13:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0167720203 for ; Mon, 9 Dec 2013 07:13:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760561Ab3LIHNe (ORCPT ); Mon, 9 Dec 2013 02:13:34 -0500 Received: from eu1sys200aog117.obsmtp.com ([207.126.144.143]:34334 "EHLO eu1sys200aog117.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760557Ab3LIHNb (ORCPT ); Mon, 9 Dec 2013 02:13:31 -0500 Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob117.postini.com ([207.126.147.11]) with SMTP ID DSNKUqVtj9ME+zTYsNHJGFvZUrSex9jH3nPy@postini.com; Mon, 09 Dec 2013 07:13:30 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 8780018E; Mon, 9 Dec 2013 07:13:14 +0000 (GMT) Received: from Webmail-ap.st.com (eapex1hubcas1.st.com [10.80.176.8]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E18891436; Mon, 9 Dec 2013 07:13:13 +0000 (GMT) Received: from localhost (10.199.81.103) by Webmail-ap.st.com (10.80.176.7) with Microsoft SMTP Server (TLS) id 8.3.297.1; Mon, 9 Dec 2013 15:13:13 +0800 Date: Mon, 9 Dec 2013 12:42:42 +0530 From: Pratyush Anand To: Arnd Bergmann Cc: Jingoo Han , Mohit KUMAR DCG , Marek Vasut , Richard Zhu , Kishon Vijay Abraham I , "linux-pci@vger.kernel.org" , Tim Harvey Subject: Re: [Query/Discussion]: IO translation with designware PCIe controller Message-ID: <20131209071241.GA5760@pratyush-vbox> References: <20131205050424.GA2298@pratyush-vbox> <201312052233.13169.arnd@arndb.de> <20131206091209.GC2298@pratyush-vbox> <201312061546.23981.arnd@arndb.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <201312061546.23981.arnd@arndb.de> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Arnd, On Fri, Dec 06, 2013 at 10:46:23PM +0800, Arnd Bergmann wrote: > On Friday 06 December 2013, Pratyush Anand wrote: > > > > [...] > > > > For example in SPEAr1340, physically RAM is mapped on above addresses. > > > > PCIe address translation unit can accept address only in the range of > > > > core addresses which are assigned to PCIe RC ie 0x80000000-0x8FFFFFFF. > > > > > > Since this is a physical address, it corresponds to address space 3 in > > > my list above, and the address you pick here is what you pass to > > > pci_ioremap_io. > > > > This is what I was expecting. But currently designware driver does not > > pass this address to pci_ioremap_io. > > OK.. We will fix it and will send patch. > > I think it does handle this correctly, look at > > static int dw_pcie_setup(int nr, struct pci_sys_data *sys) > { > ... > if (global_io_offset < SZ_1M && pp->config.io_size > 0) { > sys->io_offset = global_io_offset - pp->config.io_bus_addr; > pci_ioremap_io(sys->io_offset, pp->io.start); > global_io_offset += SZ_64K; > pci_add_resource_offset(&sys->resources, &pp->io, > sys->io_offset); > } > ... > } > > I believe this does the right thing, but you have to put the correct > translation into the 'ranges' property of the host bridge node in DT. May be not exactly. pp->io is the realio, and it is passed correctly to pci_add_resource_offset. But, as you had also said that pci_ioremap_io will receive cpu physical address space as input, therefore I think following modification will be needed to work io transaction properly. Regards Pratyush > > Arnd --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index be6ce30..cf68632 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) + global_io_offset); pp->config.io_size = resource_size(&pp->io); pp->config.io_bus_addr = range.pci_addr; + pp->io_base = range.cpu_addr; } if (restype == IORESOURCE_MEM) { of_pci_range_to_resource(&range, np, &pp->mem); @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) pp->cfg0_base = pp->cfg.start; pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; - pp->io_base = pp->io.start; pp->mem_base = pp->mem.start; pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) if (global_io_offset < SZ_1M && pp->config.io_size > 0) { sys->io_offset = global_io_offset - pp->config.io_bus_addr; - pci_ioremap_io(sys->io_offset, pp->io.start); + pci_ioremap_io(sys->io_offset, pp->io_base); global_io_offset += SZ_64K; pci_add_resource_offset(&sys->resources, &pp->io, sys->io_offset);