From patchwork Tue May 20 03:46:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 4207201 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 36EF69F32A for ; Tue, 20 May 2014 03:46:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 05AA2202FE for ; Tue, 20 May 2014 03:46:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7EEBF20304 for ; Tue, 20 May 2014 03:46:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752499AbaETDqP (ORCPT ); Mon, 19 May 2014 23:46:15 -0400 Received: from mail-ie0-f179.google.com ([209.85.223.179]:54820 "EHLO mail-ie0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750922AbaETDqP (ORCPT ); Mon, 19 May 2014 23:46:15 -0400 Received: by mail-ie0-f179.google.com with SMTP id rd18so3011370iec.24 for ; Mon, 19 May 2014 20:46:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=hxiGSfB2gCivFxDi6WgtwWPGYYzPQIdK4lkVywQ5GE0=; b=pKGFHCDAEucad2sD480L6X+4dzOVvVl8bfkhsecwpo2gNjQFo66RiILI/KlmX753mk GJV6BKV18fuU99NLkNUmwlL5PR7CjKUbByenFaUlzcLg+HRKdZ9JNGTUj3hiCi0OlXip bTfXsfrcn0FO1+a2BGy9KXLsoAhOciOixNH8nUzpQBFoPmxpwF+N/kLe33KYr2n1MxPk 6whbCmD6NF/hs8f2tF+WVrOQ5fTxH4rsSS0Bedj93fO1D3ydhTixajhmHCYEUmraaE87 wdaJCdJxga1gIYSjft61RB4nrqjpqhAlQtRcQ9hF4HhW/hDYDTJjPa0Q8dFx9+kUrUC0 LzRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:subject:to:from:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-type :content-transfer-encoding; bh=hxiGSfB2gCivFxDi6WgtwWPGYYzPQIdK4lkVywQ5GE0=; b=EnVMS23YFNWfDGvQmAHKesltJBP2Ady8b372kTX2T4E688syzVK9odXoKiOpGOOCmA VvK5g14JIfz75q/JypCktCwwZ1TSDbivJsoCOsQnoaGJwd2Uv93YbrndqZaJIpGzhjWF lHHf5viMEGoztkcNhK9CRkIdsqU+Bvql5iPyNWVHuEJ1xk00J0fk2OmMMHMDsmo/VhlL +TYTjjAuHR/NzZ4PJ8iQnN3auJCtsI7sX2uP+a2tuUgejsXYnk0pJSR8yr7dFiaMPfWH EI+B3CjnlcqA1QgglOMF8a0wvppbwwKIUslSlFO3cQaF4uIO4kCoc5kKXzchl1bQORVB ULew== X-Gm-Message-State: ALoCoQlguZtDzkXve/t7RtCqzvlnKrNgbuhHPfPS/wAAnvusuoH9sMpoY3xtckyXu499ddPBsazD X-Received: by 10.43.10.131 with SMTP id pa3mr37661290icb.18.1400557574889; Mon, 19 May 2014 20:46:14 -0700 (PDT) Received: from localhost ([172.16.49.172]) by mx.google.com with ESMTPSA id lr6sm25874215igb.15.2014.05.19.20.46.14 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 19 May 2014 20:46:14 -0700 (PDT) Subject: [PATCH v10 4/4] PCI: Add resource allocation comments To: Yinghai Lu From: Bjorn Helgaas Cc: talal@mellanox.com, Wei Yang , Gavin Shan , Benjamin Herrenschmidt , amirv@mellanox.com, eugenia@mellanox.com, Guo Chao , linux-pci@vger.kernel.org, Or Gerlitz , Jack Morgenstein Date: Mon, 19 May 2014 21:46:12 -0600 Message-ID: <20140520034612.11972.97042.stgit@bhelgaas-glaptop.roam.corp.google.com> In-Reply-To: <20140520033233.11972.49094.stgit@bhelgaas-glaptop.roam.corp.google.com> References: <20140520033233.11972.49094.stgit@bhelgaas-glaptop.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add comments in the code to match the allocation strategy of 7c671426dfc3 ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources"). No functional change. Signed-off-by: Bjorn Helgaas --- drivers/pci/setup-bus.c | 58 +++++++++++++++++++++++++++++++++++------------ drivers/pci/setup-res.c | 35 +++++++++++++++------------- 2 files changed, 62 insertions(+), 31 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index caa07fe6a23a..758ffbcf24a8 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1159,17 +1159,16 @@ void __ref __pci_bus_size_bridges(struct pci_bus *bus, additional_io_size = pci_hotplug_io_size; additional_mem_size = pci_hotplug_mem_size; } - /* - * Follow thru - */ + /* Fall through */ default: pbus_size_io(bus, realloc_head ? 0 : additional_io_size, additional_io_size, realloc_head); - /* If the bridge supports prefetchable range, size it - separately. If it doesn't, or its prefetchable window - has already been allocated by arch code, try - non-prefetchable range for both types of PCI memory - resources. */ + + /* + * If there's a 64-bit prefetchable MMIO window, compute + * the size required to put all 64-bit prefetchable + * resources in it. + */ b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES]; mask = IORESOURCE_MEM; prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; @@ -1179,29 +1178,58 @@ void __ref __pci_bus_size_bridges(struct pci_bus *bus, prefmask, prefmask, realloc_head ? 0 : additional_mem_size, additional_mem_size, realloc_head); + + /* + * If successful, all non-prefetchable resources + * and any 32-bit prefetchable resources will go in + * the non-prefetchable window. + */ if (ret == 0) { - /* - * Success, with pref mmio64, - * next will size non-pref or - * non-mmio64 */ mask = prefmask; type2 = prefmask & ~IORESOURCE_MEM_64; type3 = prefmask & ~IORESOURCE_PREFETCH; } } + + /* + * If there is no 64-bit prefetchable window, compute the + * size required to put all prefetchable resources in the + * 32-bit prefetchable window (if there is one). + */ if (!type2) { prefmask &= ~IORESOURCE_MEM_64; ret = pbus_size_mem(bus, prefmask, prefmask, prefmask, prefmask, realloc_head ? 0 : additional_mem_size, additional_mem_size, realloc_head); - if (ret == 0) { - /* Success, next will size non-prefetch. */ + + /* + * If successful, only non-prefetchable resources + * will go in the non-prefetchable window. + */ + if (ret == 0) mask = prefmask; - } else + else additional_mem_size += additional_mem_size; + type2 = type3 = IORESOURCE_MEM; } + + /* + * Compute the size required to put everything else in the + * non-prefetchable window. This includes: + * + * - all non-prefetchable resources + * - 32-bit prefetchable resources if there's a 64-bit + * prefetchable window or no prefetchable window at all + * - 64-bit prefetchable resources if there's no + * prefetchable window at all + * + * Note that the strategy in __pci_assign_resource() must + * match that used here. Specifically, we cannot put a + * 32-bit prefetchable resource in a 64-bit prefetchable + * window. + */ pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, realloc_head ? 0 : additional_mem_size, additional_mem_size, realloc_head); diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 3bdac9dc4a88..3da2542eb4df 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -209,20 +209,25 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; - /* First, try exact prefetching match.. */ + /* + * First, try exact prefetching match. Even if a 64-bit + * prefetchable bridge window is below 4GB, we can't put a 32-bit + * prefetchable resource in it because pbus_size_mem() assumes a + * 64-bit window will contain no 32-bit resources. If we assign + * things differently than they were sized, not everything will fit. + */ ret = pci_bus_alloc_resource(bus, res, size, align, min, IORESOURCE_PREFETCH | IORESOURCE_MEM_64, pcibios_align_resource, dev); if (ret == 0) return 0; + /* + * If the prefetchable window is only 32 bits wide, we can put + * 64-bit prefetchable resources in it. + */ if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { - /* - * That failed. - * - * Try 32bit pref - */ ret = pci_bus_alloc_resource(bus, res, size, align, min, IORESOURCE_PREFETCH, pcibios_align_resource, dev); @@ -230,18 +235,16 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, return 0; } - if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { - /* - * That failed. - * - * But a prefetching area can handle a non-prefetching - * window (it will just not perform as well). - * - * Also can put 64bit under 32bit range. (below 4g). - */ + /* + * If we didn't find a better match, we can put any memory resource + * in a non-prefetchable window. If this resource is 32 bits and + * non-prefetchable, the first call already tried the only possibility + * so we don't need to try again. + */ + if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, pcibios_align_resource, dev); - } + return ret; }