From patchwork Mon Jul 14 06:03:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush ANAND X-Patchwork-Id: 4542661 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BB84E9F2F4 for ; Mon, 14 Jul 2014 06:05:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D07E620158 for ; Mon, 14 Jul 2014 06:05:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E21AF2012D for ; Mon, 14 Jul 2014 06:05:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753082AbaGNGFc (ORCPT ); Mon, 14 Jul 2014 02:05:32 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:56588 "EHLO mx08-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752949AbaGNGFb (ORCPT ); Mon, 14 Jul 2014 02:05:31 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id s6E5sotY030496; Mon, 14 Jul 2014 08:04:06 +0200 Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx08-00178001.pphosted.com with ESMTP id 1n32ug15dc-1 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NOT); Mon, 14 Jul 2014 08:04:06 +0200 Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 43AEA24; Mon, 14 Jul 2014 06:03:52 +0000 (GMT) Received: from Webmail-ap.st.com (eapex1hubcas4.st.com [10.80.176.69]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 0F3D6293; Mon, 14 Jul 2014 06:03:41 +0000 (GMT) Received: from localhost (10.199.210.48) by Webmail-ap.st.com (10.80.176.7) with Microsoft SMTP Server (TLS) id 8.3.298.1; Mon, 14 Jul 2014 14:03:39 +0800 Date: Mon, 14 Jul 2014 11:33:34 +0530 From: Pratyush Anand To: Murali Karicheri Cc: "linux-arm-kernel@lists.infradead.org" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Russell King , Grant Likely , Rob Herring , Mohit KUMAR DCG , Jingoo Han , Bjorn Helgaas , Richard Zhu , Kishon Vijay Abraham I , Marek Vasut , Arnd Bergmann , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy Dunlap Subject: Re: [PATCH v4 0/6] Add Keystone PCIe controller driver Message-ID: <20140714060334.GB2930@pratyush-vbox> References: <1405110995-24676-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1405110995-24676-1-git-send-email-m-karicheri2@ti.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.12.52, 1.0.14, 0.0.0000 definitions=2014-07-13_03:2014-07-11, 2014-07-13, 1970-01-01 signatures=0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Oh.. I see my reply from gmail is not readable at all. (I forgot to switch to plain text :( ) Please ignore last mail I am replying again here. On Sat, Jul 12, 2014 at 04:36:29AM +0800, Murali Karicheri wrote: [...] > Murali Karicheri (6): > PCI: designware: add rd[wr]_other_conf API > PCI: designware: refactor MSI code to work with v3.65 dw hardware For above two you can add my reviewed-by: > PCI: designware: refactor host init code to re-use on keystone PCI > PCI: designware: enhance dw core driver to support keystone PCI host In stead of using version number and then changing few functions from static to global , I would have used same philosophy of adding callbacks wherever needed. May be maintainers can give their view, instead of patch 3 and 4 I would have gone with something like this, where kc_pcie can be passed through pp->plat_data. ~Pratyush --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 905941c..b216192 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -490,16 +490,21 @@ int __init dw_pcie_host_init(struct pcie_port *pp) } if (IS_ENABLED(CONFIG_PCI_MSI)) { - pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, - MAX_MSI_IRQS, &msi_domain_ops, - &dw_pcie_msi_chip); - if (!pp->irq_domain) { - dev_err(pp->dev, "irq domain init failed\n"); - return -ENXIO; - } + if (!pp->ops->msi_init) { + pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, + MAX_MSI_IRQS, &msi_domain_ops, + &dw_pcie_msi_chip); + if (!pp->irq_domain) { + dev_err(pp->dev, "irq domain init failed\n"); + return -ENXIO; + } - for (i = 0; i < MAX_MSI_IRQS; i++) - irq_create_mapping(pp->irq_domain, i); + for (i = 0; i < MAX_MSI_IRQS; i++) + irq_create_mapping(pp->irq_domain, i); + } else { + pp->ops->msi_init(pp, &msi_domain_ops, + &dw_pcie_msi_chip); + } } if (pp->ops->host_init) @@ -759,6 +764,9 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) BUG(); } + if (bus && pp->ops->scan_bus) + bus = pp->ops->scan_bus(pp); + return bus; } diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 387f69e..39ce496 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -52,6 +52,7 @@ struct pcie_port { struct irq_domain *irq_domain; unsigned long msi_data; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); + void *plat_data; }; struct pcie_host_ops { @@ -70,6 +71,9 @@ struct pcie_host_ops { void (*msi_set_irq)(struct pcie_port *pp, int irq); void (*msi_clear_irq)(struct pcie_port *pp, int irq); u32 (*get_msi_data)(struct pcie_port *pp); + struct pci_bus *(*scan_bus)(struct pcie_port *pp); + void (*msi_init) (struct pcie_port *pp, struct irq_domain_ops *ops, + struct msi_chip *chip); }; int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);