From patchwork Fri Oct 7 16:36:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 9366827 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 85AC760752 for ; Fri, 7 Oct 2016 16:37:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 76D9529773 for ; Fri, 7 Oct 2016 16:37:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6B77229779; Fri, 7 Oct 2016 16:37:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B96A29773 for ; Fri, 7 Oct 2016 16:37:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964812AbcJGQg7 (ORCPT ); Fri, 7 Oct 2016 12:36:59 -0400 Received: from mail.kernel.org ([198.145.29.136]:54950 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964789AbcJGQg6 (ORCPT ); Fri, 7 Oct 2016 12:36:58 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 91E342020F; Fri, 7 Oct 2016 16:36:57 +0000 (UTC) Received: from localhost (unknown [69.55.156.165]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8287C201BB; Fri, 7 Oct 2016 16:36:56 +0000 (UTC) Subject: [PATCH 01/11] PCI: hisi: Rename APB accessors To: Zhou Wang , Gabriele Paoloni From: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Date: Fri, 07 Oct 2016 11:36:54 -0500 Message-ID: <20161007163654.25540.29741.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Rename hisi_pcie_apb_readl() to hisi_apb_readl() and hisi_pcie_apb_writel() to hisi_apb_writel() for consistency with other drivers. Uninline them; there's no performance issue here, and the compiler can inline them if it's worthwhile. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-hisi.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c index 7ee9dfc..15a1167 100644 --- a/drivers/pci/host/pcie-hisi.c +++ b/drivers/pci/host/pcie-hisi.c @@ -44,15 +44,14 @@ struct hisi_pcie { struct pcie_soc_ops *soc_ops; }; -static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie, - u32 val, u32 reg) +static u32 hisi_apb_readl(struct hisi_pcie *pcie, u32 reg) { - writel(val, pcie->reg_base + reg); + return readl(pcie->reg_base + reg); } -static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg) +static void hisi_apb_writel(struct hisi_pcie *pcie, u32 val, u32 reg) { - return readl(pcie->reg_base + reg); + writel(val, pcie->reg_base + reg); } /* HipXX PCIe host only supports 32-bit config access */ @@ -66,7 +65,7 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size, walker += (where & 0x3); reg = where & ~0x3; - reg_val = hisi_pcie_apb_readl(pcie, reg); + reg_val = hisi_apb_readl(pcie, reg); if (size == 1) *val = *(u8 __force *) walker; @@ -92,15 +91,15 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size, walker += (where & 0x3); reg = where & ~0x3; if (size == 4) - hisi_pcie_apb_writel(pcie, val, reg); + hisi_apb_writel(pcie, val, reg); else if (size == 2) { - reg_val = hisi_pcie_apb_readl(pcie, reg); + reg_val = hisi_apb_readl(pcie, reg); *(u16 __force *) walker = val; - hisi_pcie_apb_writel(pcie, reg_val, reg); + hisi_apb_writel(pcie, reg_val, reg); } else if (size == 1) { - reg_val = hisi_pcie_apb_readl(pcie, reg); + reg_val = hisi_apb_readl(pcie, reg); *(u8 __force *) walker = val; - hisi_pcie_apb_writel(pcie, reg_val, reg); + hisi_apb_writel(pcie, reg_val, reg); } else return PCIBIOS_BAD_REGISTER_NUMBER; @@ -121,8 +120,7 @@ static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie) { u32 val; - val = hisi_pcie_apb_readl(hisi_pcie, PCIE_HIP06_CTRL_OFF + - PCIE_SYS_STATE4); + val = hisi_apb_readl(hisi_pcie, PCIE_HIP06_CTRL_OFF + PCIE_SYS_STATE4); return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); }