From patchwork Fri Nov 25 10:57:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 9447347 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 50A8060778 for ; Fri, 25 Nov 2016 10:57:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5346027D13 for ; Fri, 25 Nov 2016 10:57:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 484B328111; Fri, 25 Nov 2016 10:57:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5CDD527D13 for ; Fri, 25 Nov 2016 10:57:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751294AbcKYK5l (ORCPT ); Fri, 25 Nov 2016 05:57:41 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:35584 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752942AbcKYK5k (ORCPT ); Fri, 25 Nov 2016 05:57:40 -0500 Received: by mail-pf0-f194.google.com with SMTP id i88so2911480pfk.2; Fri, 25 Nov 2016 02:57:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v0lelJPgq3Tec9zD/dbucYQ5P8kVxoD7dAnQIBw5m84=; b=Mk3NyxlR2NdJAxjtpH3GfiSkXImKMYlKW5qpfF1ZKMbDp37xrtY0/3x/rR0h42aS79 dvphMzkDDmKYl35dPgsGskPMXSp6JakcxzZjJXSgnXVqnqASzrUrSGaE5mQJ/l1ycV7/ VYFLmiD+Joswt8UHqF0IcZh/0W0RU324bV9q05fiba/Lf8I0IDVyn64R+TjGL/JiwMHU otR+Z7202kdodRfMox0siubQ1tqbHHkcJRTKxl3s1FOkE32F9lu4eBaUcLpXaMUzE19f E3eD4HbsZ0+jNylJ6nGAVquLuP96+T9jYrS/3rzv000F8cevy33370aponZrclMWun/y r+PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v0lelJPgq3Tec9zD/dbucYQ5P8kVxoD7dAnQIBw5m84=; b=M015n3NDDXnmlKnsHj3fFf1kkgV8kxKQPFfWTV0DqzcMDl3lDtCZKPHCHCUWLKO2uG UmEEsv/iOjslXeuTgYgKgTf444u6xbmn7rwaCImdL9fdqzNsKo+uZgDYaWVY0g32E6pv FsFCmz8u54/Y+Kx9YcyIQIEdpGwQZgeGB69atY2u536RAt1LAyZ4wKW74H9juKu6yw+2 kFKuoPHS2Rh2vKFicOfiF8JusZddD0gzGgVtZmHqfZb9YxxwYe0sWT+W3zQ6MFaVMU5u yB3Ox+tsjLPixCGY9da6uBptJPuKtilADGGujkkkhHUTp6VfgfcMQyHzg3Wb7Yxeo5LR mpxA== X-Gm-Message-State: AKaTC001DnRiyxb1ZnK1dnClFAw0O09VbMmKNG79lraJtctcYFnu8QuvVoZxgDYIRLUDNw== X-Received: by 10.98.31.203 with SMTP id l72mr7229211pfj.74.1480071459366; Fri, 25 Nov 2016 02:57:39 -0800 (PST) Received: from localhost (port-2820.pppoe.wtnet.de. [84.46.11.15]) by smtp.gmail.com with ESMTPSA id p68sm67029207pfd.11.2016.11.25.02.57.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Nov 2016 02:57:38 -0800 (PST) From: Thierry Reding To: Bjorn Helgaas Cc: Arnd Bergmann , Tomasz Nowicki , Liviu Dudau , Lorenzo Pieralisi , Vidya Sagar , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v4 05/10] dt-bindings: pci: tegra: Add Tegra210 support Date: Fri, 25 Nov 2016 11:57:13 +0100 Message-Id: <20161125105718.3866-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161125105718.3866-1-thierry.reding@gmail.com> References: <20161125105718.3866-1-thierry.reding@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Add support for the PCI host controller found on Tegra210 SoCs. It is very similar to the variant found on Tegra124, with a couple of small differences regarding the power supplies. Signed-off-by: Thierry Reding --- .../bindings/pci/nvidia,tegra20-pcie.txt | 110 +++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index b8cc395fffea..982a74ea6df9 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -110,6 +110,20 @@ Power supplies for Tegra124: - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must supply 1.05 V. +Power supplies for Tegra210: +- Required: + - avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must + supply 1.05 V. + - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output + clocks. Must supply 1.8 V. + - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. + - dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must + supply 1.05 V. + - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3). + Must supply 3.3 V. + - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must + supply 1.8 V. + Root ports are defined as subnodes of the PCIe controller node. Required properties: @@ -436,3 +450,99 @@ Board DTS: status = "okay"; }; }; + +Tegra210: +--------- + +SoC DTSI: + + pcie-controller@01003000 { + compatible = "nvidia,tegra210-pcie"; + device_type = "pci"; + reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ + 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ + 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + + clocks = <&tegra_car TEGRA210_CLK_PCIE>, + <&tegra_car TEGRA210_CLK_AFI>, + <&tegra_car TEGRA210_CLK_PLL_E>, + <&tegra_car TEGRA210_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + +Board DTS: + + pcie-controller@01003000 { + status = "okay"; + + avdd-pll-uerefe-supply = <&avdd_1v05_pll>; + hvddio-pex-supply = <&vdd_1v8>; + dvddio-pex-supply = <&vdd_pex_1v05>; + dvdd-pex-pll-supply = <&vdd_pex_1v05>; + hvdd-pex-pll-e-supply = <&vdd_1v8>; + vddio-pex-ctl-supply = <&vdd_1v8>; + + pci@1,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; + phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; + status = "okay"; + }; + + pci@2,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; + phy-names = "pcie-0"; + status = "okay"; + }; + };