From patchwork Fri Apr 21 19:31:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 9693603 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 40EA3601D4 for ; Fri, 21 Apr 2017 19:32:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 293582865B for ; Fri, 21 Apr 2017 19:32:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1CA5E2865D; Fri, 21 Apr 2017 19:32:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 89A142865B for ; Fri, 21 Apr 2017 19:32:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1425128AbdDUTcA (ORCPT ); Fri, 21 Apr 2017 15:32:00 -0400 Received: from mail.kernel.org ([198.145.29.136]:38220 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1425125AbdDUTcA (ORCPT ); Fri, 21 Apr 2017 15:32:00 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D10D42020F; Fri, 21 Apr 2017 19:31:55 +0000 (UTC) Received: from localhost (unknown [64.22.249.253]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B8014201EF; Fri, 21 Apr 2017 19:31:51 +0000 (UTC) Subject: [PATCH 3/9] lspci: Decode AER Root Error Command, Root Error Status, Error Source From: Bjorn Helgaas To: Martin Mares Cc: linux-pci@vger.kernel.org, Jayachandran C Date: Fri, 21 Apr 2017 14:31:50 -0500 Message-ID: <20170421193150.6562.39846.stgit@bhelgaas-glaptop.roam.corp.google.com> In-Reply-To: <20170421192844.6562.30976.stgit@bhelgaas-glaptop.roam.corp.google.com> References: <20170421192844.6562.30976.stgit@bhelgaas-glaptop.roam.corp.google.com> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Bjorn Helgaas Decode the AER Root Error Command, Root Error Status, and Error Source Identification registers. Per PCIe r3.1, sec 7.10, these registers are only available for Root Ports and Root Complex Event Collectors, so we have to check the Device/Port Type from the PCIe capability. The difference in the "lspci -vv" output looks like this (for a Root Port): + RootCmd: CERptEn- NFERptEn- FERptEn- + RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd- + FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0 + ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000 Signed-off-by: Bjorn Helgaas --- lib/header.h | 13 + ls-caps.c | 16 + ls-ecaps.c | 37 +++ lspci.h | 2 tests/cap-aer-root | 626 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 682 insertions(+), 12 deletions(-) create mode 100644 tests/cap-aer-root diff --git a/lib/header.h b/lib/header.h index f031e37..03bbfa5 100644 --- a/lib/header.h +++ b/lib/header.h @@ -964,7 +964,18 @@ #define PCI_ERR_CAP_HDR_LOG 0x00001000 /* Completion Timeout Prefix/Header Log Capable */ #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ -#define PCI_ERR_ROOT_STATUS 48 +#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Error Reporting Enable */ +#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Error Reporting Enable*/ +#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Error Reporting Enable */ +#define PCI_ERR_ROOT_STATUS 48 /* Root Error Status */ +#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ +#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR Received */ +#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL Received */ +#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple ERR_FATAL/NONFATAL Received */ +#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Uncorrectable Fatal */ +#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Error Messages Received */ +#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Error Messages Received */ +#define PCI_ERR_MSG_NUM(x) (((x) >> 27) & 0x1f) /* MSI/MSI-X vector */ #define PCI_ERR_ROOT_COR_SRC 52 #define PCI_ERR_ROOT_SRC 54 diff --git a/ls-caps.c b/ls-caps.c index db45b81..30f371f 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -1125,7 +1125,7 @@ static void cap_express_slot2(struct device *d UNUSED, int where UNUSED) /* No capabilities that require this field in PCIe rev2.0 spec. */ } -static void +static int cap_express(struct device *d, int where, int cap) { int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4; @@ -1174,7 +1174,7 @@ cap_express(struct device *d, int where, int cap) } printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9); if (verbose < 2) - return; + return type; size = 16; if (slot) @@ -1182,7 +1182,7 @@ cap_express(struct device *d, int where, int cap) if (type == PCI_EXP_TYPE_ROOT_PORT) size = 32; if (!config_fetch(d, where + PCI_EXP_DEVCAP, size)) - return; + return type; cap_express_dev(d, where, type); if (link) @@ -1193,19 +1193,20 @@ cap_express(struct device *d, int where, int cap) cap_express_root(d, where); if ((cap & PCI_EXP_FLAGS_VERS) < 2) - return; + return type; size = 16; if (slot) size = 24; if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size)) - return; + return type; cap_express_dev2(d, where, type); if (link) cap_express_link2(d, where, type); if (slot) cap_express_slot2(d, where); + return type; } static void @@ -1462,6 +1463,7 @@ void show_caps(struct device *d, int where) { int can_have_ext_caps = 0; + int type = -1; if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST) { @@ -1540,7 +1542,7 @@ show_caps(struct device *d, int where) printf("Secure device \n"); break; case PCI_CAP_ID_EXP: - cap_express(d, where, cap); + type = cap_express(d, where, cap); can_have_ext_caps = 1; break; case PCI_CAP_ID_MSIX: @@ -1562,5 +1564,5 @@ show_caps(struct device *d, int where) } } if (can_have_ext_caps) - show_ext_caps(d); + show_ext_caps(d, type); } diff --git a/ls-ecaps.c b/ls-ecaps.c index 1847e8e..eae3a3d 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -90,9 +90,10 @@ cap_dsn(struct device *d, int where) } static void -cap_aer(struct device *d, int where) +cap_aer(struct device *d, int where, int type) { u32 l, l0, l1, l2, l3; + u16 w; printf("Advanced Error Reporting\n"); if (verbose < 2) @@ -143,6 +144,36 @@ cap_aer(struct device *d, int where) l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8); l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12); printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3); + + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) + { + if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12)) + return; + + l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND); + printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n", + FLAG(l, PCI_ERR_ROOT_CMD_COR_EN), + FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN), + FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN)); + + l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS); + printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n" + "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n", + FLAG(l, PCI_ERR_ROOT_COR_RCV), + FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV), + FLAG(l, PCI_ERR_ROOT_UNCOR_RCV), + FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV), + FLAG(l, PCI_ERR_ROOT_FIRST_FATAL), + FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV), + FLAG(l, PCI_ERR_ROOT_FATAL_RCV), + PCI_ERR_MSG_NUM(l)); + + w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC); + printf("\t\tErrorSrc: ERR_COR: %04x ", w); + + w = get_conf_word(d, where + PCI_ERR_ROOT_SRC); + printf("ERR_FATAL/NONFATAL: %04x\n", w); + } } static void cap_dpc(struct device *d, int where) @@ -678,7 +709,7 @@ cap_ptm(struct device *d, int where) } void -show_ext_caps(struct device *d) +show_ext_caps(struct device *d, int type) { int where = 0x100; char been_there[0x1000]; @@ -707,7 +738,7 @@ show_ext_caps(struct device *d) switch (id) { case PCI_EXT_CAP_ID_AER: - cap_aer(d, where); + cap_aer(d, where, type); break; case PCI_EXT_CAP_ID_DPC: cap_dpc(d, where); diff --git a/lspci.h b/lspci.h index a3fc9d0..9ef0919 100644 --- a/lspci.h +++ b/lspci.h @@ -68,7 +68,7 @@ void show_caps(struct device *d, int where); /* ls-ecaps.c */ -void show_ext_caps(struct device *d); +void show_ext_caps(struct device *d, int type); /* ls-caps-vendor.c */ diff --git a/tests/cap-aer-root b/tests/cap-aer-root new file mode 100644 index 0000000..c1d699f --- /dev/null +++ b/tests/cap-aer-root @@ -0,0 +1,626 @@ +00:02.0 PCI bridge: Intel Corporation Haswell-E PCI Express Root Port 2 (rev 02) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Subsystem: Intel Corporation Haswell-E PCI Express Root Port 2 + Capabilities: [60] MSI: Enable- Count=1/2 Maskable+ 64bit- + Address: 00000000 Data: 0000 + Masking: 00000000 Pending: 00000000 + Capabilities: [90] Express (v2) Root Port (Slot-), MSI 00 + DevCap: MaxPayload 256 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 256 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- + LnkCap: Port #3, Speed 8GT/s, Width x8, ASPM L1, Exit Latency L0s <512ns, L1 <16us + ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+ + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- + RootCap: CRSVisible+ + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd+ + AtomicOpsCap: Routing- 32bit+ 64bit+ 128bitCAS+ + DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd+ + AtomicOpsCtl: ReqEn- EgressBlck- + LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- + Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- + Compliance De-emphasis: -6dB + LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+ + EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest- + Capabilities: [e0] Power Management version 3 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Vendor Specific Information: ID=0002 Rev=0 Len=00c + Capabilities: [110 v1] Access Control Services + ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- + ACSCtl: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- + Capabilities: [148 v1] Advanced Error Reporting + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ + AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- + HeaderLog: 00000000 00000000 00000000 00000000 + RootCmd: CERptEn- NFERptEn- FERptEn- + RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd- + FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0 + ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000 + Capabilities: [1d0 v1] Vendor Specific Information: ID=0003 Rev=1 Len=00a + Capabilities: [250 v1] #19 + Capabilities: [280 v1] Vendor Specific Information: ID=0005 Rev=3 Len=018 + Capabilities: [300 v1] Vendor Specific Information: ID=0008 Rev=0 Len=038 +00: 86 80 04 2f 07 00 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 03 03 00 f0 00 00 20 +20: 00 be 10 c0 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 10 00 +40: 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MT27520 Family [ConnectX-3 Pro] + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR-