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Fri, 16 Jun 2017 14:14:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754001AbdFPOO2 (ORCPT ); Fri, 16 Jun 2017 10:14:28 -0400 Received: from mail-pg0-f49.google.com ([74.125.83.49]:36414 "EHLO mail-pg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753977AbdFPOO1 (ORCPT ); Fri, 16 Jun 2017 10:14:27 -0400 Received: by mail-pg0-f49.google.com with SMTP id u62so1747142pgb.3 for ; Fri, 16 Jun 2017 07:14:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ljv6UDiZTbb7mc0R4RfQCh0PB73cfbOFHAzTd8MZNTM=; b=C8rfTmStpRsaZsHaPpNVyrvMkK0KfFxvlwNJBOsHvdWn5FKglmmyA+3STz84kF7bCf F2HshhenAk3HJcdgrGp1A4p9LRSGED6N3E7H5RqZUCO6fBBZidEuf7pTnLU5RjmkJs5Z K+bRP1VmFmgnIbClfuv86hqoh+caOOCMLDziI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ljv6UDiZTbb7mc0R4RfQCh0PB73cfbOFHAzTd8MZNTM=; b=fJI2oR1IRMq3v1flnsdZlLbw1qXNI7Sz+qnKF1woyW20BBJX6VCKygXEmgVSljwsPw f3VQuOtV8XTr1tUYokpiGmpu8qaPNaym9CadcTIKeNww3n2Qtj8hirYIUnbXIE//hIFG ZHklVb4rPO9nrJikByMMr5pdgTRuIPjFfBCfL9xK/bNycdSmP0fmJmSegHKKUnP3g2Pg QjKjqXbSuT7a7TStMltJfluam747BLivwwqVSgJgUsDmyv+5oa/rrHQoRrd6g8t7niit h5LevUUMjl7hjMKv4nlywmtDPrB0TPx/MvBRN0Uy/lBtLWAV0ZogoRNq7ILMLYAAgpEz 5P0g== X-Gm-Message-State: AKS2vOzsPuOdktAQQ56HreuOSJQfnmk2GDbMcYEAP+cNVHc7sn8rWs0R SQiW71uyYQ6ZUEVJ X-Received: by 10.84.136.129 with SMTP id 1mr12892749pll.213.1497622466377; Fri, 16 Jun 2017 07:14:26 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.187]) by smtp.gmail.com with ESMTPSA id y29sm5093706pff.50.2017.06.16.07.14.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Jun 2017 07:14:25 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, arnd@arndb.de, xuejiancheng@hisilicon.com, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Xiaowei Song , Guodong Xu Subject: [PATCH v5 15/20] arm64: dts: hisi: add kirin pcie node Date: Fri, 16 Jun 2017 22:13:22 +0800 Message-Id: <20170616141322.30466-1-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-16-guodong.xu@linaro.org> References: <20170615030417.14059-16-guodong.xu@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Xiaowei Song Add PCIe node for hi3660 Cc: Guodong Xu Signed-off-by: Xiaowei Song Acked-by: Arnd Bergmann Changes in v5: * fix interrupt-map, to conform to gic's #address-cells = <0> * remove redundant status = "ok" --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 36 +++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index e138973..8183d71 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -754,5 +754,41 @@ cs-gpios = <&gpio18 5 0>; status = "disabled"; }; + + pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + }; }; };