From patchwork Thu Jul 20 23:46:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Hutchings X-Patchwork-Id: 9855821 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5BD0A601C8 for ; Thu, 20 Jul 2017 23:46:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4C55B286F7 for ; Thu, 20 Jul 2017 23:46:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 415DC2870F; Thu, 20 Jul 2017 23:46:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6ABC5286F7 for ; Thu, 20 Jul 2017 23:46:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965959AbdGTXqZ (ORCPT ); Thu, 20 Jul 2017 19:46:25 -0400 Received: from shadbolt.e.decadent.org.uk ([88.96.1.126]:49850 "EHLO shadbolt.e.decadent.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965897AbdGTXqY (ORCPT ); Thu, 20 Jul 2017 19:46:24 -0400 Received: from ben by shadbolt.decadent.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dYL93-0002E4-Ho; Fri, 21 Jul 2017 00:46:17 +0100 Date: Fri, 21 Jul 2017 00:46:13 +0100 From: Ben Hutchings To: Bjorn Helgaas Cc: Dan Carpenter , Jingoo Han , Joao Pinto , linux-pci@vger.kernel.org Message-ID: <20170720234613.GF18698@decadent.org.uk> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: ben@decadent.org.uk Subject: [PATCH] PCI: designware: Fix dw_handle_msi_irq() on 64-bit BE configs X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on shadbolt.decadent.org.uk) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit 1b497e6493c4 "PCI: dwc: Fix uninitialized variable in dw_handle_msi_irq()" fixed one problem for 64-bit architectures but left another. The find_next_bit() function assumes native ordering of bits within each word (unsigned long), so passing a pointer to a u32 variable will cause it to scan the following 32 bits on a 64-bit big-endian configuration. Alternately it could result in an alignment fault on some architectures. Copy the status to an unsigned long variable before using find_next_bit(). Fixes: 1b497e6493c4 ("PCI: dwc: Fix uninitialized variable in ...") Signed-off-by: Ben Hutchings Acked-by: Dan Carpenter --- This is compile-tested only. Ben. drivers/pci/dwc/pcie-designware-host.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index d29c020da082..511fc9188f98 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -57,6 +57,7 @@ static struct irq_chip dw_msi_irq_chip = { irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { u32 val; + unsigned long bits; int i, pos, irq; irqreturn_t ret = IRQ_NONE; @@ -65,11 +66,11 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) &val); if (!val) continue; + bits = val; ret = IRQ_HANDLED; pos = 0; - while ((pos = find_next_bit((unsigned long *) &val, 32, - pos)) != 32) { + while ((pos = find_next_bit(&bits, 32, pos)) != 32) { irq = irq_find_mapping(pp->irq_domain, i * 32 + pos); dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, 1 << pos);