From patchwork Fri Aug 18 22:56:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 9910047 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A7C2E600CC for ; Fri, 18 Aug 2017 22:56:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9935728D71 for ; Fri, 18 Aug 2017 22:56:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8BE8528D87; Fri, 18 Aug 2017 22:56:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B472728D71 for ; Fri, 18 Aug 2017 22:56:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751593AbdHRW4w (ORCPT ); Fri, 18 Aug 2017 18:56:52 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:36772 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751055AbdHRW4v (ORCPT ); Fri, 18 Aug 2017 18:56:51 -0400 Received: by mail-wm0-f44.google.com with SMTP id t201so9746422wmt.1 for ; Fri, 18 Aug 2017 15:56:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=SauqWfCBkrOUL/UJiH06sDftrW5+0zWWIEcjDeIJJkA=; b=a5yZI8wiJEO46DBZ4aSvYZJKIzio/Fc3cM1u+rVFwUCb/RZVJnKFACOBGf9W7Y59Vj sL1CUc8Yyaqu/aKfV4N5jyPNcAD6R1eGQROIeCXc2Wg1CkDGx/WUtb2RHD57dx9j8FNl 7QYs2Aa9OAALqOo1TsJ/UP+f/BtkwPsFhkO1w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=SauqWfCBkrOUL/UJiH06sDftrW5+0zWWIEcjDeIJJkA=; b=raKMtp2SnZbOeTWJYgiKBWCiZywX26Gf1RKWYm9hfGvp+VepsIoMFXEgYE3xntDqNv 1+V1JCjNzD+CYnwJJT5zntdDtXDNk71ECkne1gB+IHKHXmP/rWq7g7AYaFifGq+HGNBk eOvGRZzLn3nPzDcXhghdm0wnsPTMbD/ZjzxMmDLr8HE2tANW9w24FaGRwVoDrZhjhaWr wbmmLbyU21a+nAV6rwn+0vNQegWqfmSKVUcNFrco7Cc/QQvCypmCAIEK0BEXCJ2KmwHb 4IPcIdbTStOCzWzJpS9UiANuuyUdYuiEdY7OucFMfSnM/cHUs6Fj21cBBsdFTxPG6C4Z a3Gw== X-Gm-Message-State: AHYfb5iO9hUXFUyqBlyAdKRsur91DRb7sWYjoyFFgdzNycnqM2DpCVeg nEsZNe9FgVyM+D66NVz7Ng== X-Received: by 10.28.215.206 with SMTP id o197mr2454466wmg.40.1503097010310; Fri, 18 Aug 2017 15:56:50 -0700 (PDT) Received: from localhost.localdomain ([154.146.161.128]) by smtp.gmail.com with ESMTPSA id t135sm3161386wmt.23.2017.08.18.15.56.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Aug 2017 15:56:49 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org Cc: leif.lindholm@linaro.org, graeme.gregory@linaro.org, mw@semihalf.com, Ard Biesheuvel , Bjorn Helgaas , Jingoo Han , Joao Pinto Subject: [RFC PATCH] pci: designware: add driver for DWC controller in ECAM shift mode Date: Fri, 18 Aug 2017 23:56:38 +0100 Message-Id: <20170818225638.31563-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some implementations of the Synopsys Designware PCIe controller implement a so-called ECAM shift mode, which allows a static memory window to be configured that covers the configuration space of the entire bus range. If the firmware performs all the low level configuration that is required to expose this controller in a fully ECAM compatible manner, we can simply describe it as "pci-host-ecam-generic" and be done with it. However, it appears that in some cases (one of which is the Armada 80x0), the IP is synthesized with an ATU window size that does not allow the first bus to be mapped in a way that prevents the device on the downstream port from appearing more than once. So implement a driver that relies on the firmware to perform all low level initialization, and drives the controller in ECAM mode, but overrides the config space accessors to take the above quirk into account. Note that, unlike most drivers for this IP, this driver does not expose a fake bridge device at B/D/F 00:00.0. There is no point in doing so, given that this is not a true bridge, and does not require any windows to be configured in order for the downstream device to operate correctly. Omitting it also prevents the PCI resource allocation routines from handing out BAR space to it unnecessarily. Cc: Bjorn Helgaas Cc: Jingoo Han Cc: Joao Pinto Signed-off-by: Ard Biesheuvel --- Posted as RFC for discussion. We have systems booting with UEFI firmware that don't require yet another variation of the driver with all its low-level initialization code, given that the firmware takes care of that already for its own needs. However, it seems we cannot drive these controllers in a fully ECAM compliant mode either, and so all we need is ECAM with a quirk for the config space accessors. Kernel log capture after the patch, of a SoC with two of these puppies, one with a Realtek 8169 and one with a Renesas uPD720200. If having a patch such as this one is considered acceptable, I will create a DT binding to go with it as well. drivers/pci/dwc/Kconfig | 11 +++ drivers/pci/dwc/Makefile | 1 + drivers/pci/dwc/pcie-designware-ecam.c | 88 ++++++++++++++++++++ 3 files changed, 100 insertions(+) diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index d275aadc47ee..f2afa2c519c1 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -169,4 +169,15 @@ config PCIE_KIRIN Say Y here if you want PCIe controller support on HiSilicon Kirin series SoCs. +config PCIE_DW_HOST_ECAM + bool "Synopsys DesignWare PCIe controller in ECAM mode" + depends on OF + select PCI_HOST_COMMON + select IRQ_DOMAIN + help + Add support for Synopsys DesignWare PCIe controllers configured + by the firmware into ECAM shift mode. In some cases, these are + fully ECAM compliant, in which case the pci-host-generic driver + may be used instead. + endmenu diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile index c61be9738cce..7d5a23e5b767 100644 --- a/drivers/pci/dwc/Makefile +++ b/drivers/pci/dwc/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o +obj-$(CONFIG_PCIE_DW_HOST_ECAM) += pcie-designware-ecam.o obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),) diff --git a/drivers/pci/dwc/pcie-designware-ecam.c b/drivers/pci/dwc/pcie-designware-ecam.c new file mode 100644 index 000000000000..3ab3f88b2592 --- /dev/null +++ b/drivers/pci/dwc/pcie-designware-ecam.c @@ -0,0 +1,88 @@ +/* + * Driver for mostly ECAM compatible Synopsys dw PCIe controllers + * configured by the firmware into RC mode + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Copyright (C) 2014 ARM Limited + * Copyright (C) 2017 Linaro Limited + * + * Authors: Will Deacon + * Ard Biesheuvel + */ + +#include +#include +#include +#include +#include +#include + +static int pci_dw_ecam_config_read(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct pci_config_window *cfg = bus->sysdata; + + /* + * The Synopsys dw PCIe controller in RC mode will not filter type 0 + * config TLPs sent to devices 1 and up on its downstream port, + * resulting in devices appearing multiple times on bus 0 unless we + * filter them here. + */ + if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return pci_generic_config_read(bus, devfn, where, size, val); +} + +static int pci_dw_ecam_config_write(struct pci_bus *bus, u32 devfn, int where, + int size, u32 val) +{ + struct pci_config_window *cfg = bus->sysdata; + + if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + return pci_generic_config_write(bus, devfn, where, size, val); +} + +static struct pci_ecam_ops pci_dw_ecam_bus_ops = { + .bus_shift = 20, + .pci_ops = { + .map_bus = pci_ecam_map_bus, + .read = pci_dw_ecam_config_read, + .write = pci_dw_ecam_config_write, + } +}; + +static const struct of_device_id pci_dw_ecam_of_match[] = { + { .compatible = "snps,dw-pcie-ecam", + .data = &pci_dw_ecam_bus_ops }, + + { }, +}; + +static int pci_dw_ecam_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id; + struct pci_ecam_ops *ops; + + of_id = of_match_node(pci_dw_ecam_of_match, pdev->dev.of_node); + ops = (struct pci_ecam_ops *)of_id->data; + + return pci_host_common_probe(pdev, ops); +} + +static struct platform_driver pci_dw_ecam_driver = { + .driver = { + .name = "pci-synopsys-dw-ecam", + .of_match_table = pci_dw_ecam_of_match, + .suppress_bind_attrs = true, + }, + .probe = pci_dw_ecam_probe, +}; +builtin_platform_driver(pci_dw_ecam_driver);